Messages in this thread | | | Date | Fri, 23 May 2014 17:20:23 +0300 | From | Georgi Djakov <> | Subject | Re: [PATCH v1 3/5] clk: gcc: Add APQ8084 Global Clock Controller support |
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On 05/22/2014 08:22 PM, Stephen Boyd wrote: > On 05/22/14 09:24, Georgi Djakov wrote: >> diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c >> index 58cb2f5..c2a8d77 100644 >> --- a/drivers/clk/qcom/gcc-msm8974.c >> +++ b/drivers/clk/qcom/gcc-msm8974.c >> @@ -204,6 +204,12 @@ static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = { >> { } >> }; >> >> +static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk_apq8084[] = { >> + F(19200000, P_XO, 1, 0, 0), >> + F(50000000, P_GPLL0, 12, 0, 0), >> + { } >> +}; >> + > > Just merge this with the other blsp1_2_qup table. > >> static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { >> .cmd_rcgr = 0x0660, >> .hid_width = 5, >> @@ -768,6 +774,27 @@ static struct clk_rcg2 ce2_clk_src = { >> }, >> }; >> >> +static const struct freq_tbl ftbl_gcc_ce3_clk_apq8084[] = { >> + F(50000000, P_GPLL0, 12, 0, 0), >> + F(85710000, P_GPLL0, 7, 0, 0), >> + F(100000000, P_GPLL0, 6, 0, 0), >> + F(171430000, P_GPLL0, 3.5, 0, 0), >> + { } >> +}; >> + > > Ditto. > >> +static struct clk_rcg2 ce3_clk_src_apq8084 = { > > Please drop all the _apq8084 stuff. I imagine if we support other chips > in this same driver this won't make any sense. > >> + .cmd_rcgr = 0x1d10, >> + .hid_width = 5, >> + .parent_map = gcc_xo_gpll0_map, >> + .freq_tbl = ftbl_gcc_ce3_clk_apq8084, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "ce3_clk_src", >> + .parent_names = gcc_xo_gpll0, >> + .num_parents = 2, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> static const struct freq_tbl ftbl_gcc_gp_clk[] = { >> F(4800000, P_XO, 4, 0, 0), >> F(6000000, P_GPLL0, 10, 1, 10), >> @@ -780,6 +807,12 @@ static const struct freq_tbl ftbl_gcc_gp_clk[] = { >> { } >> }; >> >> +static const struct freq_tbl ftbl_gcc_gp_clk_apq8084[] = { >> + F(19200000, P_XO, 1, 0, 0), >> + F(100000000, P_GPLL0, 6, 0, 0), >> + F(200000000, P_GPLL0, 3, 0, 0), >> + { } >> +}; > > Merge with other GP table? > >> >> static struct clk_rcg2 gp1_clk_src = { >> .cmd_rcgr = 0x1904, >> @@ -966,6 +999,11 @@ static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { >> { } >> }; >> >> +static const struct freq_tbl ftbl_gcc_usb_hs_system_clk_apq8084[] = { >> + F(75000000, P_GPLL0, 8, 0, 0), >> + { } >> +}; >> + > > ditto. > >> static struct clk_rcg2 usb_hs_system_clk_src = { >> .cmd_rcgr = 0x0490, >> .hid_width = 5, >> @@ -1029,6 +1067,11 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { >> { } >> }; >> >> +static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk_apq8084[] = { >> + F(75000000, P_GPLL0, 8, 0, 0), >> + { } >> +}; >> + > > ditto. >
Thanks for all the comments, Stephen. I will make the appropriate changes.
BR, Georgi
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