Messages in this thread | | | Date | Mon, 19 May 2014 23:31:20 +0300 | Subject | Re: 3.13-1 dm cache possible race condition | From | roma1390 <> |
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Hello again.
Tried this on latest head: 14186fea0cb06bc43181ce239efe0df6f1af260a
Getting same error. If there is needed some additional information, please contact.
On Sun, May 18, 2014 at 6:35 PM, roma1390 <roma1390@gmail.com> wrote: > I think that somehow is got broken cache->nr_dirty > > # dmsetup status foo0 > 0 32768 cache 7/4096 1728240 256 1675650 0 0 64 64 4294967295 1 > writeback 2 migration_threshold 2048 4 random_threshold 4 > sequential_threshold 512 > > > See: 4294967295 this is -1 as is not OK. > > > Kernel: Debian stock 3.13-1-amd64 > > Actions taken: > > modprobe brd > BLOCKS=$[`blockdev --getsize64 /dev/ram0`/512] > METADATA_DEV=/dev/ram0 > CACHE_DEV=/dev/ram1 > DATA_DEV=/dev/ram2 > dmsetup create foo0 --table "0 $BLOCKS cache $METADATA_DEV $CACHE_DEV > $DATA_DEV 512 1 writeback default 0" > > Test: > one terminal window: > while true; do dd if=/dev/zero of=/dev/mapper/foo0 bs=512; done > second window: > while sleep .1; do dmsetup status foo0; done > > > after some time from 0 i get to 4294967295, which is think is not > expected value. > > > More info: > device just created: > 0 32768 cache 10/4096 1728259 256 1675650 0 0 0 64 0 1 writeback 2 > migration_threshold 2048 4 random_threshold 4 sequential_threshold 512 > after some (~20) writes: > 0 32768 cache 10/4096 1790456 256 1737543 0 0 0 64 0 1 writeback 2 > migration_threshold 2048 4 random_threshold 4 sequential_threshold 512 > started full speed test, after 2 sec: > 0 32768 cache 10/4096 2475934 256 2417479 0 0 0 64 0 1 writeback 2 > migration_threshold 2048 4 random_threshold 4 sequential_threshold 512 > 0 32768 cache 10/4096 2485872 256 2428545 0 0 0 64 5 1 writeback 2 > migration_threshold 2048 4 random_threshold 4 sequential_threshold 512 > 0 32768 cache 10/4096 2495964 256 2437959 0 0 0 64 0 1 writeback 2 > migration_threshold 2048 4 random_threshold 4 sequential_threshold 512 > 0 32768 cache 10/4096 2506447 256 2447365 0 0 0 64 20 1 writeback 2 > migration_threshold 2048 4 random_threshold 4 sequential_threshold 512 > 0 32768 cache 10/4096 2515948 256 2458439 0 0 0 64 0 1 writeback 2 > migration_threshold 2048 4 random_threshold 4 sequential_threshold 512 > 0 32768 cache 10/4096 2526687 256 2466631 0 0 0 64 0 1 writeback 2 > migration_threshold 2048 4 random_threshold 4 sequential_threshold 512 > after ~10sec: > 0 32768 cache 10/4096 2667754 256 2609991 0 0 0 64 0 1 writeback 2 > migration_threshold 2048 4 random_threshold 4 sequential_threshold 512 > 0 32768 cache 10/4096 2678571 256 2618183 0 0 0 64 4294967295 1 > writeback 2 migration_threshold 2048 4 random_threshold 4 > sequential_threshold 512 > 0 32768 cache 10/4096 2687846 256 2630471 0 0 0 64 4294967295 1 > writeback 2 migration_threshold 2048 4 random_threshold 4 > sequential_threshold 512 > 0 32768 cache 10/4096 2698349 256 2638663 0 0 0 64 4294967295 1 > writeback 2 migration_threshold 2048 4 random_threshold 4 > sequential_threshold 512 > 0 32768 cache 10/4096 2708082 256 2648514 0 0 0 64 5 1 writeback 2 > migration_threshold 2048 4 random_threshold 4 sequential_threshold 512 > 0 32768 cache 10/4096 2717700 256 2659143 0 0 0 64 4294967295 1 > writeback 2 migration_threshold 2048 4 random_threshold 4 > sequential_threshold 512 > 0 32768 cache 10/4096 2728596 256 2667335 0 0 0 64 4294967295 1 > writeback 2 migration_threshold 2048 4 random_threshold 4 > sequential_threshold 512 > 0 32768 cache 10/4096 2737453 256 2679623 0 0 0 64 4294967295 1 > writeback 2 migration_threshold 2048 4 random_threshold 4 > sequential_threshold 512 > ^C
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