Messages in this thread | | | Date | Tue, 9 Dec 2014 11:19:40 +0100 | From | Arend van Spriel <> | Subject | Re: using DMA-API on ARM |
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On 12/08/14 18:01, Arend van Spriel wrote: > On 12/08/14 17:03, Catalin Marinas wrote: >> On Mon, Dec 08, 2014 at 03:01:32PM +0000, Arnd Bergmann wrote: >>> [ 0.000000] PL310 OF: cache setting yield illegal associativity >>> [ 0.000000] PL310 OF: -1069781724 calculated, only 8 and 16 legal >>> [ 0.000000] L2C-310 enabling early BRESP for Cortex-A9 >>> [ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9 >>> [ 0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled >>> [ 0.000000] L2C-310 cache controller enabled, 16 ways, 256 kB >>> [ 0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x4e130001 >> >> If the above value is correct, they should make sure bit 22 is set in >> AUX_CTRL. > > Hante applied the patch and it now says: > > [ 0.000000] PL310 OF: cache setting yield illegal associativity > [ 0.000000] PL310 OF: -1069781724 calculated, only 8 and 16 legal > [ 0.000000] L2C-310 enabling early BRESP for Cortex-A9 > [ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9 > [ 0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled > [ 0.000000] L2C-310 cache controller enabled, 16 ways, 256 kB > [ 0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x4e530001 > > He started running a test overnight. So will see if it hits the failure > with this L2 cache configuration.
The issue did not trigger overnight so it seems setting bit 22 <Shared Attribute _Override_ Enable> solves the issue over here. Now the question is how to move forward with this. As I understood from Catalin this patch was not included as it was not considered responsibility of the linux kernel.
Regards, Arend
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