Messages in this thread | | | Date | Thu, 11 Dec 2014 10:39:20 +0000 | From | Will Deacon <> | Subject | Re: [PATCH 2/2] misc: sram: switch to ioremap_wc from ioremap |
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On Thu, Dec 11, 2014 at 10:08:33AM +0000, Philipp Zabel wrote: > Hi Abhilash, > > Am Donnerstag, den 11.12.2014, 08:28 +0530 schrieb Abhilash Kesavan: > > Currently, the SRAM allocator returns device memory via ioremap. > > This causes issues on ARM64 when the internal SoC SRAM allocated by > > the generic sram driver is used for audio playback. The destination > > buffer address (which is ioremapped SRAM) is not 64-bit aligned for > > certain streams (e.g. 44.1k sampling rate). In such cases we get > > unhandled alignment faults. Use ioremap_wc in place of ioremap which > > gives us normal non-cacheable memory instead of device memory. > > Could this break the omap_bus_sync() implementation in > arch/arm/mach-omap2/omap4-common.c? > > void omap_bus_sync(void) > { > if (dram_sync && sram_sync) { > writel_relaxed(readl_relaxed(dram_sync), dram_sync); > writel_relaxed(readl_relaxed(sram_sync), sram_sync); > isb(); > } > } > > It is used in wmb() and omap_do_wfi() to drain interconnect write > buffers on omap4/5. If sram_sync is mapped with write-combining, could > the last write to sram_sync stay stuck in the write-combining buffer > until after the function returns?
I think you have that issue anyway, since you can get an early write response even if you use ioremap. Does the write to sram_sync have side-effects that we need to wait for?
Will
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