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SubjectRe: [PATCH V5 05/12] mailbox: Add NVIDIA Tegra XUSB mailbox driver
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On 18 November 2014 at 04:11, Andrew Bresticker <abrestic@chromium.org> wrote:

> +
> +static int tegra_xusb_mbox_send_data(struct mbox_chan *chan, void *data)
> +{
> + struct tegra_xusb_mbox *mbox = to_tegra_mbox(chan->mbox);
> + struct tegra_xusb_mbox_msg *msg = data;
> + unsigned long flags;
> + u32 reg, owner;
> +
> + dev_dbg(mbox->mbox.dev, "TX message %#x:%#x\n", msg->cmd, msg->data);
> +
> + /* ACK/NAK must be sent with the controller as the mailbox owner */
> + if (msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)
> + owner = MBOX_OWNER_FW;
> + else
> + owner = MBOX_OWNER_SW;
> +
> + spin_lock_irqsave(&mbox->lock, flags);
> +
> + /* Acquire mailbox */
> + if (mbox_readl(mbox, XUSB_CFG_ARU_MBOX_OWNER) != MBOX_OWNER_NONE) {
> + dev_err(mbox->mbox.dev, "Mailbox not idle\n");
> + goto busy;
> + }
> + mbox_writel(mbox, owner, XUSB_CFG_ARU_MBOX_OWNER);
> + if (mbox_readl(mbox, XUSB_CFG_ARU_MBOX_OWNER) != owner) {
> + dev_err(mbox->mbox.dev, "Failed to acquire mailbox");
> + goto busy;
> + }
> +
> + mbox_writel(mbox, mbox_pack_msg(msg), XUSB_CFG_ARU_MBOX_DATA_IN);
> + reg = mbox_readl(mbox, XUSB_CFG_ARU_MBOX_CMD);
> + reg |= MBOX_INT_EN | MBOX_DEST_FALC;
> + mbox_writel(mbox, reg, XUSB_CFG_ARU_MBOX_CMD);
> +
> + spin_unlock_irqrestore(&mbox->lock, flags);
> +
> + return 0;
> +busy:
> + spin_unlock_irqrestore(&mbox->lock, flags);
> + return -EBUSY;
> +}
> +
> +static int tegra_xusb_mbox_startup(struct mbox_chan *chan)
> +{
> + return 0;
> +}
> +
> +static void tegra_xusb_mbox_shutdown(struct mbox_chan *chan)
> +{
> +}
> +
> +static bool tegra_xusb_mbox_last_tx_done(struct mbox_chan *chan)
> +{
> + /*
> + * Transmissions are assumed to be completed as soon as they are
> + * written to the mailbox.
> + */
> + return true;
>
In .send_data() you you mark the channel busy by setting the
XUSB_CFG_ARU_MBOX_OWNER to !MBOX_OWNER_NONE, which remains so until
you get an IRQ. So maybe you should check for the OWNER_NONE flag in
.last_tx_done()?

-Jassi


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