Messages in this thread | | | Date | Tue, 28 Oct 2014 11:03:53 -0700 | Subject | Re: [RFC PATCH 1/2] zap_pte_range: update addr when forcing flush after TLB batching faiure | From | Linus Torvalds <> |
| |
On Tue, Oct 28, 2014 at 10:07 AM, Will Deacon <will.deacon@arm.com> wrote: > > I don't think that's necessarily true, at least not on the systems I'm > familiar with. A table walk can be comparatively expensive, particularly > when virtualisation is involved and the depth of the host and guest page > tables starts to grow -- we're talking >20 memory accesses per walk. By > contrast, the TLB invalidation messages are asynchronous and carried on > the interconnect (a DSB instruction is used to synchronise the updates).
">20 memory accesses per *walk*"? Isn't the ARM a regular table? So once you've gone down to the pte level, it's just an array, regardless of how many levels there are.
But I guess there are no actual multi-socket ARM's around in real life, so you probably don't see the real scaling costs. Within a die, you're probably right that the overhead is negligible.
Linus
| |