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    SubjectRe: [PATCH v2 2/3] ARM: dts: socfpga: fpga bridges bindings docs
    Hi!

    On Thu, Oct 23, 2014 at 06:51:06PM -0500, atull@opensource.altera.com wrote:
    > From: Alan Tull <atull@opensource.altera.com>

    (...)

    > diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
    > new file mode 100644
    > index 0000000..bc24a2e
    > --- /dev/null
    > +++ b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
    > @@ -0,0 +1,53 @@
    > +Altera FPGA/HPS Bridge Driver
    > +
    > +This driver manages a bridge between a FPGA and a host processor system (HPS).
    > +User space can enable or disable the bridge by writing a "1" or a "0",
    > +respectively, to its enable file under bridge's entry in
    > +/sys/class/fpga-bridge. Typically, one disables the bridges before
    > +reprogramming the FPGA. Once the FPGA is reprogrammed, the bridges are
    > +reenabled.
    > +

    NAK.

    This is all linux specific and doesn't belong here.

    > +Required properties:
    > +
    > + - compatible : should contain one of:
    > + "altr,socfpga-hps2fpga-bridge"
    > + "altr,socfpga-lwhps2fpga-bridge"
    > + "altr,socfpga-fpga2hps-bridge"
    > +
    > + - clocks : clocks used by this module
    > +
    > + - altr,l3-syscon : phandle of the l3 interconnect module
    > +

    L3 shouldn't be a syscon. Have you tried dumping the regmap in the debugfs if L3
    is a syscon? Doesn't work.

    > +Optional properties:
    > + - label : name that you want this bridge to show up as under
    > + /sys/class/fpga-bridge. Default is br<device#> if this is
    > + not specified.
    > +

    Why? Linux-specific.

    > + - init-val : 0 if driver should disable bridge at startup
    > + 1 if driver should enable bridge at startup
    > + driver leaves bridge in current state if property not
    > + specified.
    > +

    Configuration in the DT? Really?

    > +Example:
    > + hps_fpgabridge0: fpgabridge@0 {
    > + compatible = "altr,socfpga-hps2fpga-bridge";
    > + label = "hps2fpga";
    > + altr,l3-syscon = <&l3regs>;
    > + clocks = <&l4_main_clk>;
    > + init-val = <1>;
    > + };
    > +
    > + hps_fpgabridge1: fpgabridge@1 {
    > + compatible = "altr,socfpga-lwhps2fpga-bridge";
    > + label = "lwhps2fpga";
    > + altr,l3-syscon = <&l3regs>;
    > + clocks = <&l4_main_clk>;
    > + init-val = <0>;
    > + };
    > +
    > + hps_fpgabridge2: fpgabridge@2 {
    > + compatible = "altr,socfpga-fpga2hps-bridge";
    > + label = "fpga2hps";
    > + altr,l3-syscon = <&l3regs>;
    > + clocks = <&l4_main_clk>;
    > + };

    The bridges are the buses into the FPGA. This has to be accomodated.
    The bridges have two specified memory ranges: one the address space
    of the bus, the second the register space for configuration.

    This binding does NOT correctly describe the hardware. Sorry.

    Regards,
    Steffen

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