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    Subject[PATCH 3.10 129/129] arm64: Use Normal NonCacheable memory for writecombine
    Date
    3.10-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Catalin Marinas <catalin.marinas@arm.com>

    commit 4f00130b70e5eee813cc7bc298e0f3fdf79673cc upstream.

    This provides better performance compared to Device GRE and also allows
    unaligned accesses. Such memory is intended to be used with standard RAM
    (e.g. framebuffers) and not I/O.

    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
    Cc: Mark Brown <broonie@kernel.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/arm64/include/asm/pgtable.h | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/arch/arm64/include/asm/pgtable.h
    +++ b/arch/arm64/include/asm/pgtable.h
    @@ -184,7 +184,7 @@ static inline void set_pte_at(struct mm_
    #define pgprot_noncached(prot) \
    __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE))
    #define pgprot_writecombine(prot) \
    - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_GRE))
    + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
    #define pgprot_dmacoherent(prot) \
    __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
    #define __HAVE_PHYS_MEM_ACCESS_PROT



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