Messages in this thread | | | Date | Fri, 31 Jan 2014 12:27:39 +0000 | From | srinivas kandagatla <> | Subject | Re: [PATCH 1/4] ARM: STi: add stid127 soc support |
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Hi Arnd, On 30/01/14 18:39, Arnd Bergmann wrote: > Actually reading the code in this file shows that the L2 cache > initialization is the only nonstandard thing in there. We should > really find a way to get rid of the entire function. I think this will get rid of lot of code left in board-dt.
> > Sorry if I missed the initial review, but can you explain > why this is needed to start with? On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set the way-size explicit here.
Thanks, srini
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