Messages in this thread | | | From | Jingoo Han <> | Subject | Re: [PATCH V3] PCI: exynos: add support for MSI | Date | Thu, 26 Sep 2013 13:32:18 +0900 |
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On Friday, September 06, 2013 3:55 PM, Jingoo Han wrote: > > This patch adds support for Message Signaled Interrupt in the > Exynos PCIe diver using Synopsys designware PCIe core IP. > > Signed-off-by: Siva Reddy Kallam <siva.kallam@samsung.com> > Signed-off-by: Srikanth T Shivanand <ts.srikanth@samsung.com> > Signed-off-by: Jingoo Han <jg1.han@samsung.com> > Cc: Pratyush Anand <pratyush.anand@st.com> > Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Hi Bjorn Helgaas,
There is no comment for last 3 weeks. Would you merge this patch to your tree? Thank you.
Best regards, Jingoo Han
> --- > Changes since v2: > - fixed MAX_MSI_CTRLS because MAX_MSI_IRQS is 32 only > - used __get_free_pages() to allocate msi_data > - used one msi_data and msi_irq_in_use per one RC > - used irq_domain to represent the MSI controller > - removed msi-base irq number from device tree because this is not > a hardware property. > > Changes since v1: > - removed unnecessary exynos_pcie_clear_irq_level() > - updated the bindings documentation > - used new msi_chip infrastructure > - removed ARCH_SUPPORTS_MSI > - replaced #ifdef guards with IS_ENABLED(CONFIG_PCI_MSI) > > drivers/pci/host/pci-exynos.c | 44 +++++++ > drivers/pci/host/pcie-designware.c | 240 ++++++++++++++++++++++++++++++++++++ > drivers/pci/host/pcie-designware.h | 14 +++ > 3 files changed, 298 insertions(+)
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