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SubjectRe: [PATCH V3] pci: exynos: split into two parts such as Synopsys part and Exynos part
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On Tuesday 23 July 2013, Jingoo Han wrote:
> >
> > Also I have one more query.
> > In your dt binding, your pci address and cpu address is the same. But the pci
> > address should start at 0x00000000 and end at 0xffffffff (for 32bit). Shouldn't
> > the cpu address map to something within this range of pci address?

The size is limited by the window available (e.g. 0x80000000-0x8FFFFFFF), it can
never be the full 4GB on a 32 bit non-LPAE system. If you only care about memory
space here (in practice you want at least also config space) that means you could
either have an identity map

<0x82000000 0 0x80000000 0x80000000 0 0x1fffffff>;

or use bus address 0

<0x82000000 0 0 0x80000000 0 0x1fffffff>;

but the length is always limited by the upstream bus.

> Sorry, I cannot answer it exactly.
> DT binding was confirmed by Arnd Bergmann.
> He will answer it exactly.

Normally you want the pci and cpu addresses to be the same, i.e. identity mapped.
This simplifies PCI bus master DMA as it ensures that there is no aliasing between
PCI memory space and RAM addresses visible to the host.

If you know that there is never any RAM at CPU address 0, you can also make the
PCI memory space be mapped from bus address 0, which has the advantage of allowing
access to low PCI addresses, e.g. for legacy VGA output using the 0xa0000-0xbffff
range, but it's less common. In particular on x86 there is always an identity
mapping.

The driver should be able to handle any mapping that can be described by the binding
and is physically possible to be programmed into the translation windows.

Arnd


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