Messages in this thread Patch in this message | | | Date | Tue, 16 Jul 2013 16:19:35 +0800 | From | Hein Tibosch <> | Subject | [PATCH] i2c-omap: always send stop after nack |
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Hi Vikram,
On a OMAP4460, i2c-bus-3:
A driver (lm75) is causing many 'timeout waiting for bus ready' errors. SDA remains high (as it should), but SCL remains low after a NACK. The bus becomes _unusable for other clients_.
While probing, "lm75" writes a command, followed by a read + stop, but the write command is NACK'd. The chip does accept other writes/reads, it just refuses to ack invalid commands.
Can you tell me if the patch below would make any sense? Or is it the responsibility of the client to reset the i2c_smbus?
In case of M_IGNORE_NAK there is no problem, a STOP will follow after the last command.
Thanks, Hein
Signed-off-by: Hein Tibosch <hein_tibosch@yahoo.es>
--- drivers/i2c/busses/i2c-omap.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index e02f9e3..2f7a712 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -615,11 +615,9 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap, if (dev->cmd_err & OMAP_I2C_STAT_NACK) { if (msg->flags & I2C_M_IGNORE_NAK) return 0; - if (stop) { - w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); - w |= OMAP_I2C_CON_STP; - omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); - } + w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); + w |= OMAP_I2C_CON_STP; + omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); return -EREMOTEIO; } return -EIO; -- 1.7.9.5
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