Messages in this thread | | | Date | Mon, 15 Jul 2013 07:54:12 -0700 | From | Greg KH <> | Subject | Re: [PATCH RFC] trafgen: xilinx: add axi traffic generator driver |
| |
On Mon, Jul 15, 2013 at 05:09:48PM +0530, Srikanth Thokala wrote: > This is the driver for AXI Traffic Generator IP. The AXI > Traffic Generator IP is a core that stresses the AXI4 > interconnect and other AXI4 peripherals in the system. > It generates a wide variety of AXI4 transactions based on > the core programming. > > Architecture of the core is broadly separated into a master > and slave block, each of which contains the write block and > read block. Other support functions are provided by the > control registers and three internal RAMs - Master RAM, > Command RAM, Parameter RAM. The initialisation sequence > includes programming Command RAM with commands, data into > Master RAM (optional Parameter RAM programming) and then > enable master logic using control register interface. > This sequence generates traffic to cores connected in the > h/w design. > > The driver for this IP is designed to be a module with > sysfs interface. All the control registers and internal > RAMs can be accessed through sysfs interface. > > NOTE: All the sysfs functions need to be documented > as per kernel-doc format.
Please do that so we can properly understand the api you are creating here.
thanks,
greg k-h
| |