Messages in this thread | | | From | "Jongsung Kim" <> | Subject | RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5 | Date | Thu, 16 May 2013 22:26:41 +0900 |
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Stephen Warren <swarren@wwwdotorg.org> : >> All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011 >> TRM: >> >> r1p4-r1p5 Contains the following differences in functionality: >> * The receive and transmit FIFOs are increased to a depth of 32. >> * The Revision field in the UARTPeriphID2 Register on page 3-24 >> bits [7:4] now reads back as 0x3. > > Well, that certainly isn't true in practice. I think we should revert > this commit until we can determine what the problem is.
I asked to the ARM support about this. Waiting for reply..
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