Messages in this thread | | | Date | Sun, 28 Apr 2013 10:56:28 +0200 | From | Sebastian Hesselbarth <> | Subject | Re: [PATCH 1/2] clk: si5351: Fix clkout rate computation. |
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On 04/23/2013 08:22 AM, Marek Belisko wrote: > Rate was incorrectly computed because we read from wrong divider register. > > Signed-off-by: Marek Belisko<marek.belisko@streamunlimited.com>
Marek,
sorry for the late reply and very good catch!
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> --- > drivers/clk/clk-si5351.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c > index 8927284..cf39e53 100644 > --- a/drivers/clk/clk-si5351.c > +++ b/drivers/clk/clk-si5351.c > @@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw, > unsigned char reg; > unsigned char rdiv; > > - if (hwdata->num> 5) > + if (hwdata->num<= 5) > reg = si5351_msynth_params_address(hwdata->num) + 2; > else > reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
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