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    Subject[PATCH 05/11] perf list: Update documentation about raw event setup
    Date
    From: Robert Richter <robert.richter@amd.com>

    It was missing that only certain bit fields are passed to the config
    value which confused users. Updating it.

    Signed-off-by: Robert Richter <robert.richter@amd.com>
    Cc: Ingo Molnar <mingo@kernel.org>
    Link: http://lkml.kernel.org/r/1344361396-7237-6-git-send-email-robert.richter@amd.com
    Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
    ---
    tools/perf/Documentation/perf-list.txt | 6 ++++++
    1 file changed, 6 insertions(+)

    diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt
    index ddc2252..232be51 100644
    --- a/tools/perf/Documentation/perf-list.txt
    +++ b/tools/perf/Documentation/perf-list.txt
    @@ -15,6 +15,7 @@ DESCRIPTION
    This command displays the symbolic event types which can be selected in the
    various perf commands with the -e option.

    +[[EVENT_MODIFIERS]]
    EVENT MODIFIERS
    ---------------

    @@ -44,6 +45,11 @@ layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Softwar
    of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
    Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).

    +Note: Only the following bit fields can be set in x86 counter
    +registers: event, umask, edge, inv, cmask. Esp. guest/host only and
    +OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
    +MODIFIERS>>.
    +
    Example:

    If the Intel docs for a QM720 Core i7 describe an event as:
    --
    1.7.9.2.358.g22243
    --
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