Messages in this thread | | | Date | Fri, 17 Aug 2012 10:46:02 +0100 | From | Catalin Marinas <> | Subject | Re: [PATCH v2 30/31] arm64: Build infrastructure |
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On Fri, Aug 17, 2012 at 10:32:13AM +0100, Tony Lindgren wrote: > * Catalin Marinas <catalin.marinas@arm.com> [120814 11:00]: > > --- /dev/null > > +++ b/arch/arm64/Kconfig > > @@ -0,0 +1,261 @@ > > +config ARM64 > > + def_bool y > > + select OF > > + select OF_EARLY_FLATTREE > > + select IRQ_DOMAIN > > + select HAVE_AOUT > > + select HAVE_DMA_ATTRS > > + select HAVE_DMA_API_DEBUG > > + select HAVE_IDE > > + select HAVE_MEMBLOCK > > + select RTC_LIB > > + select SYS_SUPPORTS_APM_EMULATION > > + select HAVE_GENERIC_DMA_COHERENT > > + select GENERIC_IOMAP > > + select HAVE_IRQ_WORK > > + select HAVE_PERF_EVENTS > > + select HAVE_ARCH_TRACEHOOK > > + select PERF_USE_VMALLOC > > + select HAVE_HW_BREAKPOINT if PERF_EVENTS > > + select HAVE_GENERIC_HARDIRQS > > + select GENERIC_HARDIRQS_NO_DEPRECATED > > + select HAVE_SPARSE_IRQ > > + select SPARSE_IRQ > > + select GENERIC_IRQ_SHOW > > + select GENERIC_SMP_IDLE_THREAD > > + select NO_BOOTMEM > > + help > > + ARM 64-bit (AArch64) Linux support. > > Anything we should select here for ARM generic timers and > interrupts assuming we can always expect to boot using those?
There is an entry in drivers/clocksource/Kconfig:
config CLKSRC_ARM_GENERIC def_bool y if ARM64
I will have something similar for the GIC but the model does not currently support GICv3 to be able to test. I'll publish a branch with example SoC code (for the model) and that adds GIC support into drivers/irqchip/ with the address information from FDT. The per-CPU GIC initialisation is done via a CPU notifier to decouple this from the SoC code (I think even on 32-bit ARM it could be done in the same way, gic_secondary_init() always takes 0 as argument.
-- Catalin
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