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    Subject[PATCH v2 1/2] drivers/mfd: Add realtek pcie card reader driver
    Date
    From: Wei WANG <wei_wang@realsil.com.cn>

    Realtek PCI-E card reader driver adapts requests from upper-level
    sdmmc/memstick layer to the real physical card reader.

    Signed-off-by: Wei WANG <wei_wang@realsil.com.cn>
    Reviewed-by: Arnd Bergmann <arnd@arndb.de>
    ---
    drivers/mfd/Kconfig | 9 +
    drivers/mfd/Makefile | 4 +
    drivers/mfd/rts5209.c | 102 +++
    drivers/mfd/rts5229.c | 117 ++++
    drivers/mfd/rtsx_pcr.c | 1464 +++++++++++++++++++++++++++++++++++++++
    drivers/mfd/rtsx_pcr.h | 31 +
    include/linux/mfd/rtsx_common.h | 47 ++
    include/linux/mfd/rtsx_pci.h | 692 ++++++++++++++++++
    8 files changed, 2466 insertions(+)
    create mode 100644 drivers/mfd/rts5209.c
    create mode 100644 drivers/mfd/rts5229.c
    create mode 100644 drivers/mfd/rtsx_pcr.c
    create mode 100644 drivers/mfd/rtsx_pcr.h
    create mode 100644 include/linux/mfd/rtsx_common.h
    create mode 100644 include/linux/mfd/rtsx_pci.h

    diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
    index d1facef..4c07a34 100644
    --- a/drivers/mfd/Kconfig
    +++ b/drivers/mfd/Kconfig
    @@ -63,6 +63,15 @@ config MFD_SM501_GPIO
    lines on the SM501. The platform data is used to supply the
    base number for the first GPIO line to register.

    +config MFD_RTSX_PCI
    + tristate "Support for Realtek PCI-E driver-based card reader"
    + depends on PCI
    + help
    + This supports for Realtek PCI-Express driver-based card reader including
    + rts5209, rts5229, etc. Realtek driver-based card reader supports access
    + to many types of memory cards, such as Memory Stick, Memory Stick Pro,
    + Secure Digital and MultiMediaCard.
    +
    config MFD_ASIC3
    bool "Support for Compaq ASIC3"
    depends on GENERIC_HARDIRQS && GPIOLIB && ARM
    diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
    index 79dd22d..e8cdc7b 100644
    --- a/drivers/mfd/Makefile
    +++ b/drivers/mfd/Makefile
    @@ -9,6 +9,9 @@ obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
    obj-$(CONFIG_MFD_SM501) += sm501.o
    obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o

    +rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o
    +obj-$(CONFIG_MFD_RTSX_PCI) += rtsx_pci.o
    +
    obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
    obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o
    obj-$(CONFIG_HTC_I2CPLD) += htc-i2cpld.o
    @@ -132,3 +135,4 @@ obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o
    obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o
    obj-$(CONFIG_MFD_ANATOP) += anatop-mfd.o
    obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o
    +obj-$(CONFIG_MFD_RTSX_PCI) += rtsx_pci.o
    diff --git a/drivers/mfd/rts5209.c b/drivers/mfd/rts5209.c
    new file mode 100644
    index 0000000..6e23568
    --- /dev/null
    +++ b/drivers/mfd/rts5209.c
    @@ -0,0 +1,102 @@
    +/* Driver for Realtek PCI-Express card reader
    + *
    + * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
    + *
    + * This program is free software; you can redistribute it and/or modify it
    + * under the terms of the GNU General Public License as published by the
    + * Free Software Foundation; either version 2, or (at your option) any
    + * later version.
    + *
    + * This program is distributed in the hope that it will be useful, but
    + * WITHOUT ANY WARRANTY; without even the implied warranty of
    + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
    + * General Public License for more details.
    + *
    + * You should have received a copy of the GNU General Public License along
    + * with this program; if not, see <http://www.gnu.org/licenses/>.
    + *
    + * Author:
    + * Wei WANG <wei_wang@realsil.com.cn>
    + * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
    + */
    +
    +#include <linux/module.h>
    +#include <linux/mfd/rtsx_pci.h>
    +
    +static u8 rts5209_get_ic_version(struct rtsx_pcr *pcr)
    +{
    + u8 val;
    +
    + val = rtsx_pci_readb(pcr, 0x1C);
    + return val & 0x0F;
    +}
    +
    +static int rts5209_extra_init_hw(struct rtsx_pcr *pcr)
    +{
    + return 0;
    +}
    +
    +static int rts5209_optimize_phy(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_write_phy_register(pcr, 0x00, 0xB966);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +static int rts5209_turn_on_led(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_write_register(pcr, 0xFD58, 0x01, 0x00);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +static int rts5209_turn_off_led(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_write_register(pcr, 0xFD58, 0x01, 0x01);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +static int rts5209_enable_auto_blink(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +static int rts5209_disable_auto_blink(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +const struct pcr_ops rts5209_pcr_ops = {
    + .get_ic_version = rts5209_get_ic_version,
    + .extra_init_hw = rts5209_extra_init_hw,
    + .optimize_phy = rts5209_optimize_phy,
    + .turn_on_led = rts5209_turn_on_led,
    + .turn_off_led = rts5209_turn_off_led,
    + .enable_auto_blink = rts5209_enable_auto_blink,
    + .disable_auto_blink = rts5209_disable_auto_blink,
    +};
    diff --git a/drivers/mfd/rts5229.c b/drivers/mfd/rts5229.c
    new file mode 100644
    index 0000000..85fc8a2
    --- /dev/null
    +++ b/drivers/mfd/rts5229.c
    @@ -0,0 +1,117 @@
    +/* Driver for Realtek PCI-Express card reader
    + *
    + * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
    + *
    + * This program is free software; you can redistribute it and/or modify it
    + * under the terms of the GNU General Public License as published by the
    + * Free Software Foundation; either version 2, or (at your option) any
    + * later version.
    + *
    + * This program is distributed in the hope that it will be useful, but
    + * WITHOUT ANY WARRANTY; without even the implied warranty of
    + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
    + * General Public License for more details.
    + *
    + * You should have received a copy of the GNU General Public License along
    + * with this program; if not, see <http://www.gnu.org/licenses/>.
    + *
    + * Author:
    + * Wei WANG <wei_wang@realsil.com.cn>
    + * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
    + */
    +
    +#include <linux/module.h>
    +#include <linux/mfd/rtsx_pci.h>
    +
    +static u8 rts5229_get_ic_version(struct rtsx_pcr *pcr)
    +{
    + u8 val;
    +
    + rtsx_pci_read_register(pcr, 0xFE90, &val);
    + return val & 0x0F;
    +}
    +
    +static int rts5229_extra_init_hw(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + rtsx_pci_init_cmd(pcr);
    +
    + /* Switch LDO3318 source from DV33 to card_3v3 */
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 0xFE78, 0x03, 0x00);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 0xFE78, 0x03, 0x01);
    + /* LED shine disabled, set initial shine cycle period */
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 0xFC1E, 0x0F, 0x02);
    +
    + err = rtsx_pci_send_cmd(pcr, 100);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +static int rts5229_optimize_phy(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + /* Optimize RX sensitivity */
    + err = rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +static int rts5229_turn_on_led(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_write_register(pcr, 0xFC1F, 0x02, 0x02);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +static int rts5229_turn_off_led(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_write_register(pcr, 0xFC1F, 0x02, 0x00);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +static int rts5229_enable_auto_blink(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_write_register(pcr, 0xFC1E, 0x08, 0x08);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +static int rts5229_disable_auto_blink(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_write_register(pcr, 0xFC1E, 0x08, 0x00);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +const struct pcr_ops rts5229_pcr_ops = {
    + .get_ic_version = rts5229_get_ic_version,
    + .extra_init_hw = rts5229_extra_init_hw,
    + .optimize_phy = rts5229_optimize_phy,
    + .turn_on_led = rts5229_turn_on_led,
    + .turn_off_led = rts5229_turn_off_led,
    + .enable_auto_blink = rts5229_enable_auto_blink,
    + .disable_auto_blink = rts5229_disable_auto_blink,
    +};
    diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c
    new file mode 100644
    index 0000000..ce13dac
    --- /dev/null
    +++ b/drivers/mfd/rtsx_pcr.c
    @@ -0,0 +1,1464 @@
    +/* Driver for Realtek PCI-Express card reader
    + *
    + * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
    + *
    + * This program is free software; you can redistribute it and/or modify it
    + * under the terms of the GNU General Public License as published by the
    + * Free Software Foundation; either version 2, or (at your option) any
    + * later version.
    + *
    + * This program is distributed in the hope that it will be useful, but
    + * WITHOUT ANY WARRANTY; without even the implied warranty of
    + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
    + * General Public License for more details.
    + *
    + * You should have received a copy of the GNU General Public License along
    + * with this program; if not, see <http://www.gnu.org/licenses/>.
    + *
    + * Author:
    + * Wei WANG <wei_wang@realsil.com.cn>
    + * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
    + */
    +
    +#include <linux/pci.h>
    +#include <linux/module.h>
    +#include <linux/dma-mapping.h>
    +#include <linux/highmem.h>
    +#include <linux/delay.h>
    +#include <linux/interrupt.h>
    +#include <linux/idr.h>
    +#include <linux/platform_device.h>
    +#include <linux/mfd/rtsx_pci.h>
    +#include <asm/unaligned.h>
    +
    +#include "rtsx_pcr.h"
    +
    +static bool msi_en = true;
    +module_param(msi_en, bool, S_IRUGO | S_IWUSR);
    +MODULE_PARM_DESC(msi_en, "Enable MSI");
    +
    +static struct workqueue_struct *workqueue;
    +static DEFINE_IDR(rtsx_pci_idr);
    +static DEFINE_SPINLOCK(rtsx_pci_lock);
    +
    +static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
    + { 0x10EC, 0x5209, PCI_ANY_ID, PCI_ANY_ID,
    + PCI_CLASS_OTHERS << 16, 0xFF0000 },
    + { 0x10EC, 0x5229, PCI_ANY_ID, PCI_ANY_ID,
    + PCI_CLASS_OTHERS << 16, 0xFF0000 },
    + { 0, }
    +};
    +
    +MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
    +
    +void rtsx_pci_start_run(struct rtsx_pcr *pcr)
    +{
    + /* If pci device removed, don't queue idle work any more */
    + if (pcr->remove_pci)
    + return;
    +
    + if (pcr->state != PDEV_STAT_RUN) {
    + pcr->state = PDEV_STAT_RUN;
    + pcr->ops->enable_auto_blink(pcr);
    + }
    +
    + mod_timer(&pcr->idle_timer, jiffies + msecs_to_jiffies(200));
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
    +
    +int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
    +{
    + int i;
    + u32 val = 3 << 30;
    +
    + val |= (u32)(addr & 0x3FFF) << 16;
    + val |= (u32)mask << 8;
    + val |= (u32)data;
    +
    + rtsx_pci_writel(pcr, RTSX_HAIMR, val);
    +
    + for (i = 0; i < MAX_RW_REG_CNT; i++) {
    + val = rtsx_pci_readl(pcr, RTSX_HAIMR);
    + if ((val & (1 << 31)) == 0) {
    + if (data != (u8)val)
    + return -EIO;
    + return 0;
    + }
    + }
    +
    + return -ETIMEDOUT;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
    +
    +int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
    +{
    + u32 val = 2 << 30;
    + int i;
    +
    + val |= (u32)(addr & 0x3FFF) << 16;
    + rtsx_pci_writel(pcr, RTSX_HAIMR, val);
    +
    + for (i = 0; i < MAX_RW_REG_CNT; i++) {
    + val = rtsx_pci_readl(pcr, RTSX_HAIMR);
    + if ((val & (1 << 31)) == 0)
    + break;
    + }
    +
    + if (i >= MAX_RW_REG_CNT)
    + return -ETIMEDOUT;
    +
    + if (data)
    + *data = (u8)(val & 0xFF);
    +
    + return 0;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
    +
    +int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
    +{
    + int err, i, finished = 0;
    + u8 tmp;
    +
    + rtsx_pci_init_cmd(pcr);
    +
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
    +
    + err = rtsx_pci_send_cmd(pcr, 100);
    + if (err < 0)
    + return err;
    +
    + for (i = 0; i < 100000; i++) {
    + err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
    + if (err < 0)
    + return err;
    +
    + if (!(tmp & 0x80)) {
    + finished = 1;
    + break;
    + }
    + }
    +
    + if (!finished)
    + return -ETIMEDOUT;
    +
    + return 0;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
    +
    +int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
    +{
    + int err, i, finished = 0;
    + u16 data = 0;
    + u8 *ptr, tmp;
    +
    + rtsx_pci_init_cmd(pcr);
    +
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
    +
    + err = rtsx_pci_send_cmd(pcr, 100);
    + if (err < 0)
    + return err;
    +
    + for (i = 0; i < 100000; i++) {
    + err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
    + if (err < 0)
    + return err;
    +
    + if (!(tmp & 0x80)) {
    + finished = 1;
    + break;
    + }
    + }
    +
    + if (!finished)
    + return -ETIMEDOUT;
    +
    + rtsx_pci_init_cmd(pcr);
    +
    + rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
    + rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
    +
    + err = rtsx_pci_send_cmd(pcr, 100);
    + if (err < 0)
    + return err;
    +
    + ptr = rtsx_pci_get_cmd_data(pcr);
    + data = ((u16)ptr[1] << 8) | ptr[0];
    +
    + if (val)
    + *val = data;
    +
    + return 0;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
    +
    +void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
    +{
    + rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
    + rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
    +
    + rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
    + rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
    +
    +void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
    + u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
    +{
    + unsigned long flags;
    + u32 val = 0;
    + u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
    +
    + val |= (u32)(cmd_type & 0x03) << 30;
    + val |= (u32)(reg_addr & 0x3FFF) << 16;
    + val |= (u32)mask << 8;
    + val |= (u32)data;
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    + ptr += pcr->ci;
    + if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
    + put_unaligned_le32(val, ptr);
    + ptr++;
    + pcr->ci++;
    + }
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
    +
    +void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
    +{
    + u32 val = 1 << 31;
    +
    + rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
    +
    + val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
    + /* Hardware Auto Response */
    + val |= 0x40000000;
    + rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
    +
    +int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
    +{
    + struct completion trans_done;
    + u32 val = 1 << 31;
    + long timeleft;
    + unsigned long flags;
    + int err = 0;
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    +
    + /* set up data structures for the wakeup system */
    + pcr->done = &trans_done;
    + pcr->trans_result = TRANS_NOT_READY;
    + init_completion(&trans_done);
    + pcr->trans_state = STATE_TRANS_CMD;
    +
    + rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
    +
    + val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
    + /* Hardware Auto Response */
    + val |= 0x40000000;
    + rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
    +
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    + /* Wait for TRANS_OK_INT */
    + timeleft = wait_for_completion_interruptible_timeout(
    + &trans_done, msecs_to_jiffies(timeout));
    + if (timeleft <= 0) {
    + dev_dbg(&(pcr->pci->dev), "pcr->int_reg = 0x%x\n",
    + pcr->int_reg);
    + err = -ETIMEDOUT;
    + goto finish_send_cmd;
    + }
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    + if (pcr->trans_result == TRANS_RESULT_FAIL)
    + err = -EINVAL;
    + else if (pcr->trans_result == TRANS_RESULT_OK)
    + err = 0;
    + else if (pcr->trans_result == TRANS_NO_DEVICE)
    + err = -ENODEV;
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    +finish_send_cmd:
    + spin_lock_irqsave(&pcr->lock, flags);
    + pcr->done = NULL;
    + pcr->trans_state = STATE_TRANS_NONE;
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    + if ((err < 0) && (err != -ENODEV))
    + rtsx_pci_stop_cmd(pcr);
    +
    + if (pcr->finish_me)
    + complete(pcr->finish_me);
    +
    + return err;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
    +
    +/**
    + * The length field is 20-bit long. So if the buffer length is
    + * longer than 0x80000, this function will divide the buffer into
    + * several small buffers to ensure the length field won't overflow.
    + */
    +static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
    + u32 addr, u32 len, u8 option)
    +{
    + u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr);
    + u64 val = 0;
    + u32 temp_len = 0;
    + u8 temp_opt = 0;
    +
    + ptr += pcr->sgi;
    + do {
    + if (len > 0x80000) {
    + temp_len = 0x80000;
    + temp_opt = option & (~SG_END);
    + } else {
    + temp_len = len;
    + temp_opt = option;
    + }
    + val = ((u64)addr << 32) | ((u64)temp_len << 12) | temp_opt;
    +
    + if (pcr->sgi < (HOST_SG_TBL_BUF_LEN / 8)) {
    + put_unaligned_le64(val, ptr);
    + ptr++;
    + pcr->sgi++;
    + }
    +
    + len -= temp_len;
    + addr += temp_len;
    + } while (len);
    +}
    +
    +static int rtsx_pci_transfer_sglist_adma(struct rtsx_pcr *pcr,
    + struct scatterlist *sg, int num_sg, int read, int timeout)
    +{
    + struct completion trans_done;
    + u8 dir;
    + int buf_cnt, i;
    + int err = 0;
    + long timeleft;
    + unsigned long flags;
    + struct scatterlist *sg_ptr;
    + enum dma_data_direction dma_dir;
    +
    + if ((sg == NULL) || (num_sg <= 0))
    + return -EINVAL;
    +
    + if (read) {
    + dir = DEVICE_TO_HOST;
    + dma_dir = DMA_FROM_DEVICE;
    + } else {
    + dir = HOST_TO_DEVICE;
    + dma_dir = DMA_TO_DEVICE;
    + }
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    +
    + /* set up data structures for the wakeup system */
    + pcr->done = &trans_done;
    + pcr->trans_state = STATE_TRANS_SG;
    + pcr->trans_result = TRANS_NOT_READY;
    +
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    + buf_cnt = dma_map_sg(&(pcr->pci->dev), sg, num_sg, dma_dir);
    +
    + sg_ptr = sg;
    + for (i = 0; i <= buf_cnt / (HOST_SG_TBL_BUF_LEN / 8); i++) {
    + u32 val = TRIG_DMA;
    + int sg_cnt, j;
    +
    + if (i == buf_cnt / (HOST_SG_TBL_BUF_LEN / 8))
    + sg_cnt = buf_cnt % (HOST_SG_TBL_BUF_LEN / 8);
    + else
    + sg_cnt = (HOST_SG_TBL_BUF_LEN / 8);
    +
    + pcr->sgi = 0;
    + for (j = 0; j < sg_cnt; j++) {
    + dma_addr_t addr = sg_dma_address(sg_ptr);
    + unsigned int len = sg_dma_len(sg_ptr);
    + u8 option;
    +
    + dev_dbg(&(pcr->pci->dev),
    + "DMA addr: 0x%x, Len: 0x%x\n",
    + (unsigned int)addr, len);
    +
    + if (j == (sg_cnt - 1))
    + option = SG_VALID | SG_END | SG_TRANS_DATA;
    + else
    + option = SG_VALID | SG_TRANS_DATA;
    +
    + rtsx_pci_add_sg_tbl(pcr, (u32)addr, (u32)len, option);
    + sg_ptr = sg_next(sg_ptr);
    + }
    +
    + dev_dbg(&(pcr->pci->dev), "SG table count = %d\n", pcr->sgi);
    +
    + val |= (u32)(dir & 0x01) << 29;
    + val |= ADMA_MODE;
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    +
    + init_completion(&trans_done);
    +
    + rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
    + rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
    +
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    + timeleft = wait_for_completion_interruptible_timeout(
    + &trans_done, msecs_to_jiffies(timeout));
    + if (timeleft <= 0) {
    + dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
    + __func__, __LINE__);
    + err = -ETIMEDOUT;
    + goto out;
    + }
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    + if (pcr->trans_result == TRANS_RESULT_FAIL) {
    + err = -EINVAL;
    + spin_unlock_irqrestore(&pcr->lock, flags);
    + goto out;
    + } else if (pcr->trans_result == TRANS_NO_DEVICE) {
    + err = -ENODEV;
    + spin_unlock_irqrestore(&pcr->lock, flags);
    + goto out;
    + }
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    + sg_ptr += sg_cnt;
    + }
    +
    + /* Wait for TRANS_OK_INT */
    + spin_lock_irqsave(&pcr->lock, flags);
    + if (pcr->trans_result == TRANS_NOT_READY) {
    + init_completion(&trans_done);
    + spin_unlock_irqrestore(&pcr->lock, flags);
    + timeleft = wait_for_completion_interruptible_timeout(
    + &trans_done, msecs_to_jiffies(timeout));
    + if (timeleft <= 0) {
    + dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
    + __func__, __LINE__);
    + err = -ETIMEDOUT;
    + goto out;
    + }
    + } else {
    + spin_unlock_irqrestore(&pcr->lock, flags);
    + }
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    + if (pcr->trans_result == TRANS_RESULT_FAIL)
    + err = -EINVAL;
    + else if (pcr->trans_result == TRANS_RESULT_OK)
    + err = 0;
    + else if (pcr->trans_result == TRANS_NO_DEVICE)
    + err = -ENODEV;
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    +out:
    + spin_lock_irqsave(&pcr->lock, flags);
    + pcr->done = NULL;
    + pcr->trans_state = STATE_TRANS_NONE;
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    + dma_unmap_sg(&(pcr->pci->dev), sg, num_sg, dma_dir);
    +
    + if ((err < 0) && (err != -ENODEV))
    + rtsx_pci_stop_cmd(pcr);
    +
    + if (pcr->finish_me)
    + complete(pcr->finish_me);
    +
    + return err;
    +}
    +
    +static int rtsx_pci_transfer_buf(struct rtsx_pcr *pcr,
    + void *buf, size_t len, int read, int timeout)
    +{
    + struct completion trans_done;
    + dma_addr_t addr;
    + u8 dir;
    + int err = 0;
    + u32 val = (1 << 31);
    + long timeleft;
    + unsigned long flags;
    + enum dma_data_direction dma_dir;
    +
    + if ((buf == NULL) || (len <= 0))
    + return -EINVAL;
    +
    + if (read) {
    + dir = DEVICE_TO_HOST;
    + dma_dir = DMA_FROM_DEVICE;
    + } else {
    + dir = HOST_TO_DEVICE;
    + dma_dir = DMA_TO_DEVICE;
    + }
    +
    + addr = dma_map_single(&(pcr->pci->dev), buf, len, dma_dir);
    + if (!addr)
    + return -EINVAL;
    +
    + val |= (u32)(dir & 0x01) << 29;
    + val |= (u32)(len & 0x00FFFFFF);
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    +
    + /* set up data structures for the wakeup system */
    + pcr->done = &trans_done;
    +
    + init_completion(&trans_done);
    +
    + pcr->trans_state = STATE_TRANS_BUF;
    + pcr->trans_result = TRANS_NOT_READY;
    +
    + rtsx_pci_writel(pcr, RTSX_HDBAR, addr);
    + rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
    +
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    + /* Wait for TRANS_OK_INT */
    + timeleft = wait_for_completion_interruptible_timeout(&trans_done,
    + msecs_to_jiffies(timeout));
    + if (timeleft <= 0) {
    + dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
    + __func__, __LINE__);
    + err = -ETIMEDOUT;
    + goto out;
    + }
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    + if (pcr->trans_result == TRANS_RESULT_FAIL)
    + err = -EINVAL;
    + else if (pcr->trans_result == TRANS_RESULT_OK)
    + err = 0;
    + else if (pcr->trans_result == TRANS_NO_DEVICE)
    + err = -ENODEV;
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    +out:
    + spin_lock_irqsave(&pcr->lock, flags);
    + pcr->done = NULL;
    + pcr->trans_state = STATE_TRANS_NONE;
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    + dma_unmap_single(&(pcr->pci->dev), addr, len, dma_dir);
    +
    + if ((err < 0) && (err != -ENODEV))
    + rtsx_pci_stop_cmd(pcr);
    +
    + if (pcr->finish_me)
    + complete(pcr->finish_me);
    +
    + return err;
    +}
    +
    +int rtsx_pci_transfer_data(struct rtsx_pcr *pcr,
    + void *buf, size_t len, int use_sg, int read, int timeout)
    +{
    + int err = 0;
    +
    + dev_dbg(&(pcr->pci->dev), "use_sg = %d\n", use_sg);
    +
    + /* don't transfer data during abort processing */
    + if (pcr->remove_pci)
    + return -EINVAL;
    +
    + if (use_sg) {
    + err = rtsx_pci_transfer_sglist_adma(pcr,
    + (struct scatterlist *)buf, use_sg,
    + read, timeout);
    + } else {
    + err = rtsx_pci_transfer_buf(pcr, buf, len, read, timeout);
    + }
    +
    + return err;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
    +
    +int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
    +{
    + int err;
    + int i, j;
    + u16 reg;
    + u8 *ptr;
    +
    + if (buf_len > 512)
    + buf_len = 512;
    +
    + ptr = buf;
    + reg = PPBUF_BASE2;
    + for (i = 0; i < buf_len / 256; i++) {
    + rtsx_pci_init_cmd(pcr);
    +
    + for (j = 0; j < 256; j++)
    + rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
    +
    + err = rtsx_pci_send_cmd(pcr, 250);
    + if (err < 0)
    + return err;
    +
    + memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
    + ptr += 256;
    + }
    +
    + if (buf_len % 256) {
    + rtsx_pci_init_cmd(pcr);
    +
    + for (j = 0; j < buf_len % 256; j++)
    + rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
    +
    + err = rtsx_pci_send_cmd(pcr, 250);
    + if (err < 0)
    + return err;
    + }
    +
    + memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
    +
    + return 0;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
    +
    +int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
    +{
    + int err;
    + int i, j;
    + u16 reg;
    + u8 *ptr;
    +
    + if (buf_len > 512)
    + buf_len = 512;
    +
    + ptr = buf;
    + reg = PPBUF_BASE2;
    + for (i = 0; i < buf_len / 256; i++) {
    + rtsx_pci_init_cmd(pcr);
    +
    + for (j = 0; j < 256; j++) {
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
    + reg++, 0xFF, *ptr);
    + ptr++;
    + }
    +
    + err = rtsx_pci_send_cmd(pcr, 250);
    + if (err < 0)
    + return err;
    + }
    +
    + if (buf_len % 256) {
    + rtsx_pci_init_cmd(pcr);
    +
    + for (j = 0; j < buf_len % 256; j++) {
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
    + reg++, 0xFF, *ptr);
    + ptr++;
    + }
    +
    + err = rtsx_pci_send_cmd(pcr, 250);
    + if (err < 0)
    + return err;
    + }
    +
    + return 0;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
    +
    +static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
    +{
    + int err;
    +
    + rtsx_pci_init_cmd(pcr);
    +
    + while (*tbl & 0xFFFF0000) {
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
    + (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
    + tbl++;
    + }
    +
    + err = rtsx_pci_send_cmd(pcr, 100);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +int rtsx_pci_sd_pull_ctl_enable(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_set_pull_ctl(pcr, pcr->sd_pull_ctl_enable_tbl);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_sd_pull_ctl_enable);
    +
    +int rtsx_pci_sd_pull_ctl_disable(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + err = rtsx_pci_set_pull_ctl(pcr, pcr->sd_pull_ctl_disable_tbl);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_sd_pull_ctl_disable);
    +
    +static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
    +{
    + u32 reg = 0;
    +
    + reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
    +
    + reg |= SD_INT_EN | SD_OC_INT_EN;
    +
    + /* Enable Bus Interrupt */
    + rtsx_pci_writel(pcr, RTSX_BIER, reg);
    +
    + dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", reg);
    +}
    +
    +static inline u8 double_ssc_depth(u8 depth)
    +{
    + return ((depth > 1) ? (depth - 1) : depth);
    +}
    +
    +static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
    +{
    + if (div > CLK_DIV_1) {
    + if (ssc_depth > (div - 1))
    + ssc_depth -= (div - 1);
    + else
    + ssc_depth = SSC_DEPTH_4M;
    + }
    +
    + return ssc_depth;
    +}
    +
    +int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
    + u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
    +{
    + int err, clk;
    + u8 N, min_N, max_N, clk_divider;
    + u8 mcu_cnt, div, max_div;
    + u8 depth[] = {
    + [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
    + [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
    + [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
    + [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
    + [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
    + };
    +
    + if (initial_mode) {
    + /* We use 250k(around) here, in initial stage */
    + clk_divider = SD_CLK_DIVIDE_128;
    + card_clock = 30000000;
    + } else {
    + clk_divider = SD_CLK_DIVIDE_0;
    + }
    + err = rtsx_pci_write_register(pcr, SD_CFG1,
    + SD_CLK_DIVIDE_MASK, clk_divider);
    + if (err < 0)
    + return err;
    +
    + card_clock /= 1000000;
    + dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
    +
    + min_N = 80;
    + max_N = 208;
    + max_div = CLK_DIV_8;
    +
    + clk = card_clock;
    + if (!initial_mode && double_clk)
    + clk = card_clock * 2;
    + dev_dbg(&(pcr->pci->dev), "Internal SSC clock: %dMHz\n", clk);
    +
    + N = (u8)(clk - 2);
    + if ((clk <= 2) || (N > max_N))
    + return -EINVAL;
    +
    + mcu_cnt = (u8)(125/clk + 3);
    + if (mcu_cnt > 15)
    + mcu_cnt = 15;
    +
    + /* Make sure that the SSC clock div_n is equal or greater than min_N */
    + div = CLK_DIV_1;
    + while ((N < min_N) && (div < max_div)) {
    + N = (N + 2) * 2 - 2;
    + div++;
    + }
    + dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div);
    +
    + ssc_depth = depth[ssc_depth];
    + if (double_clk)
    + ssc_depth = double_ssc_depth(ssc_depth);
    +
    + ssc_depth = revise_ssc_depth(ssc_depth, div);
    + dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
    +
    + rtsx_pci_init_cmd(pcr);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
    + CLK_LOW_FREQ, CLK_LOW_FREQ);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
    + 0xFF, (div << 4) | mcu_cnt);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
    + SSC_DEPTH_MASK, ssc_depth);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
    + if (vpclk) {
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
    + PHASE_NOT_RESET, 0);
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
    + PHASE_NOT_RESET, PHASE_NOT_RESET);
    + }
    +
    + err = rtsx_pci_send_cmd(pcr, 2000);
    + if (err < 0)
    + return err;
    +
    + /* Wait SSC clock stable */
    + udelay(10);
    + err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
    +
    +void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
    +{
    + struct completion finish;
    +
    + pcr->finish_me = &finish;
    + init_completion(&finish);
    +
    + if (pcr->done)
    + complete(pcr->done);
    +
    + if (!pcr->remove_pci)
    + rtsx_pci_stop_cmd(pcr);
    +
    + wait_for_completion_interruptible_timeout(&finish,
    + msecs_to_jiffies(2));
    + pcr->finish_me = NULL;
    +}
    +EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
    +
    +static struct platform_device *rtsx_pci_create_subdev(struct rtsx_pcr *pcr,
    + const char *name, int slot_id)
    +{
    + struct platform_device *p_dev;
    + int err;
    +
    + p_dev = platform_device_alloc(name, pcr->id);
    + if (p_dev == NULL) {
    + dev_dbg(&(pcr->pci->dev), "alloc platform device fail!\n");
    + return NULL;
    + }
    +
    + p_dev->dev.parent = &(pcr->pci->dev);
    + platform_set_drvdata(p_dev, pcr);
    + pcr->slots[slot_id].p_dev = p_dev;
    +
    + err = platform_device_add(p_dev);
    + if (err) {
    + dev_dbg(&(pcr->pci->dev), "add platform device fail!\n");
    + pcr->slots[slot_id].p_dev = NULL;
    + platform_device_put(p_dev);
    + return NULL;
    + }
    +
    + return p_dev;
    +}
    +
    +static void rtsx_pci_card_detect(struct work_struct *work)
    +{
    + struct delayed_work *dwork;
    + struct rtsx_pcr *pcr;
    + unsigned long flags;
    + u32 irq_status;
    +
    + dwork = to_delayed_work(work);
    + pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
    +
    + dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    +
    + irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
    + dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
    +
    + if (pcr->need_release) {
    + /* Card unplugged */
    + dev_dbg(&(pcr->pci->dev), "need_release: 0x%x\n",
    + pcr->need_release);
    +
    + if (pcr->need_release & SD_EXIST) {
    + pcr->need_release &= ~SD_EXIST;
    + spin_unlock_irqrestore(&pcr->lock, flags);
    + if (pcr->slots[RTSX_SD_SLOT].p_dev) {
    + platform_device_unregister(
    + pcr->slots[RTSX_SD_SLOT].p_dev);
    + pcr->slots[RTSX_SD_SLOT].p_dev = NULL;
    + }
    + spin_lock_irqsave(&pcr->lock, flags);
    + }
    + }
    +
    + if (pcr->need_reset) {
    + /* Card plugged in */
    + pcr->need_reset &= irq_status;
    + if (!pcr->need_reset)
    + goto out;
    +
    + dev_dbg(&(pcr->pci->dev), "need_reset: 0x%x\n",
    + pcr->need_reset);
    +
    + if (pcr->need_reset & SD_EXIST) {
    + pcr->need_reset &= ~SD_EXIST;
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +
    + pcr->slots[RTSX_SD_SLOT].p_dev =
    + rtsx_pci_create_subdev(pcr,
    + DRV_NAME_RTSX_PCI_SDMMC, RTSX_SD_SLOT);
    +
    + spin_lock_irqsave(&pcr->lock, flags);
    + }
    + }
    +
    +out:
    + spin_unlock_irqrestore(&pcr->lock, flags);
    +}
    +
    +static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
    +{
    + struct rtsx_pcr *pcr = dev_id;
    + u32 int_enable, int_reg;
    +
    + if (!pcr)
    + return IRQ_NONE;
    +
    + spin_lock(&pcr->lock);
    +
    + int_enable = rtsx_pci_readl(pcr, RTSX_BIER);
    + int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
    + /* Clear interrupt flag */
    + rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
    + if ((int_reg & int_enable) == 0) {
    + spin_unlock(&pcr->lock);
    + return IRQ_NONE;
    + }
    + if (int_reg == 0xFFFFFFFF) {
    + spin_unlock(&pcr->lock);
    + return IRQ_HANDLED;
    + }
    +
    + int_reg &= (int_enable | 0x7FFFFF);
    +
    + if (int_reg & SD_INT) {
    + if (int_reg & SD_EXIST) {
    + pcr->need_reset |= SD_EXIST;
    + } else {
    + pcr->need_release |= SD_EXIST;
    + pcr->need_reset &= ~SD_EXIST;
    + }
    + }
    +
    + if (pcr->need_reset || pcr->need_release)
    + queue_delayed_work(workqueue, &pcr->carddet_work,
    + msecs_to_jiffies(200));
    +
    + if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
    + if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
    + pcr->trans_result = TRANS_RESULT_FAIL;
    + if (pcr->done)
    + complete(pcr->done);
    + } else if (int_reg & TRANS_OK_INT) {
    + pcr->trans_result = TRANS_RESULT_OK;
    + if (pcr->done)
    + complete(pcr->done);
    + } else if (int_reg & DATA_DONE_INT) {
    + pcr->trans_result = TRANS_NOT_READY;
    + if (pcr->done && (pcr->trans_state == STATE_TRANS_SG))
    + complete(pcr->done);
    + }
    + }
    +
    + spin_unlock(&pcr->lock);
    + return IRQ_HANDLED;
    +}
    +
    +static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
    +{
    + dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
    + __func__, pcr->msi_en, pcr->pci->irq);
    +
    + if (request_irq(pcr->pci->irq, rtsx_pci_isr,
    + pcr->msi_en ? 0 : IRQF_SHARED,
    + DRV_NAME_RTSX_PCR, pcr)) {
    + dev_err(&(pcr->pci->dev),
    + "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
    + pcr->pci->irq);
    + return -1;
    + }
    +
    + pcr->irq = pcr->pci->irq;
    + pci_intx(pcr->pci, !pcr->msi_en);
    +
    + return 0;
    +}
    +
    +static void rtsx_pci_enter_idle(unsigned long __data)
    +{
    + struct rtsx_pcr *pcr = (struct rtsx_pcr *)__data;
    +
    + queue_work(workqueue, &pcr->idle_work);
    +}
    +
    +static void rtsx_pci_idle_work(struct work_struct *work)
    +{
    + struct rtsx_pcr *pcr = container_of(work, struct rtsx_pcr, idle_work);
    +
    + dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
    +
    + mutex_lock(&pcr->pcr_mutex);
    +
    + pcr->state = PDEV_STAT_IDLE;
    +
    + pcr->ops->disable_auto_blink(pcr);
    + pcr->ops->turn_off_led(pcr);
    +
    + mutex_unlock(&pcr->pcr_mutex);
    +}
    +
    +static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
    +{
    + int err;
    +
    + rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
    +
    + rtsx_pci_enable_bus_int(pcr);
    +
    + /* Power on SSC */
    + err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
    + if (err < 0)
    + return err;
    +
    + /* Wait SSC power stable */
    + udelay(200);
    +
    + err = pcr->ops->optimize_phy(pcr);
    + if (err < 0)
    + return err;
    +
    + rtsx_pci_init_cmd(pcr);
    +
    + /* Set mcu_cnt to 7 to ensure data can be sampled properly */
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
    +
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
    + /* Disable card clock */
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
    + /* Reset ASPM state to default value */
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
    + /* Card driving select */
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
    + SD30_DRIVE_SEL, 0x07, DRIVER_TYPE_D);
    + /* Enlarge the estimation window of PERST# glitch
    + * to reduce the chance of invalid card interrupt
    + */
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
    + /* Update RC oscillator to 400k
    + * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
    + * 1: 2M 0: 400k
    + */
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
    + /* Set interrupt write clear
    + * bit 1: U_elbi_if_rd_clr_en
    + * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
    + * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
    + */
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
    + /* Force CLKREQ# PIN to drive 0 to request clock */
    + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
    +
    + err = rtsx_pci_send_cmd(pcr, 100);
    + if (err < 0)
    + return err;
    +
    + err = pcr->ops->extra_init_hw(pcr);
    + if (err < 0)
    + return err;
    +
    + return 0;
    +}
    +
    +/* SD Pull Control Enable:
    + * SD_DAT[3:0] ==> pull up
    + * SD_CD ==> pull up
    + * SD_WP ==> pull up
    + * SD_CMD ==> pull up
    + * SD_CLK ==> pull down
    + */
    +static const u32 rts5209_sd_pull_ctl_enable_tbl[] = {
    + RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
    + RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
    + RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
    + 0,
    +};
    +
    +static const u32 rts5229_sd_pull_ctl_enable_tbl1[] = {
    + RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
    + RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
    + 0,
    +};
    +
    +/* For RTS5229 version C */
    +static const u32 rts5229_sd_pull_ctl_enable_tbl2[] = {
    + RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
    + RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD9),
    + 0,
    +};
    +
    +/* SD Pull Control Disable:
    + * SD_DAT[3:0] ==> pull down
    + * SD_CD ==> pull up
    + * SD_WP ==> pull down
    + * SD_CMD ==> pull down
    + * SD_CLK ==> pull down
    + */
    +static const u32 rts5209_sd_pull_ctl_disable_tbl[] = {
    + RTSX_REG_PAIR(CARD_PULL_CTL1, 0x55),
    + RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
    + RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
    + 0,
    +};
    +
    +static const u32 rts5229_sd_pull_ctl_disable_tbl1[] = {
    + RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
    + RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
    + 0,
    +};
    +
    +/* For RTS5229 version C */
    +static const u32 rts5229_sd_pull_ctl_disable_tbl2[] = {
    + RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
    + RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE5),
    + 0,
    +};
    +
    +static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
    +{
    + int err;
    + u32 irq_status;
    +
    + spin_lock_init(&pcr->lock);
    + mutex_init(&pcr->pcr_mutex);
    +
    + switch (PCI_PID(pcr)) {
    + default:
    + case 0x5209:
    + pcr->extra_caps = EXTRA_CAPS_SD_SDR50 |
    + EXTRA_CAPS_SD_SDR104 | EXTRA_CAPS_MMC_8BIT;
    +
    + pcr->rval.ldo_pwr_on = 0x00;
    + pcr->rval.ldo_pwr_off = 0x06;
    + pcr->rval.ldo_pwr_suspend = 0x04;
    +
    + pcr->num_slots = 1;
    + pcr->ops = &rts5209_pcr_ops;
    +
    + pcr->ic_version = pcr->ops->get_ic_version(pcr);
    + pcr->sd_pull_ctl_enable_tbl = rts5209_sd_pull_ctl_enable_tbl;
    + pcr->sd_pull_ctl_disable_tbl = rts5209_sd_pull_ctl_disable_tbl;
    +
    + break;
    +
    + case 0x5229:
    + pcr->extra_caps = EXTRA_CAPS_SD_SDR50 |
    + EXTRA_CAPS_SD_SDR104;
    +
    + pcr->rval.ldo_pwr_on = 0x06;
    + pcr->rval.ldo_pwr_off = 0x00;
    + pcr->rval.ldo_pwr_suspend = 0x02;
    +
    + pcr->num_slots = 1;
    + pcr->ops = &rts5229_pcr_ops;
    +
    + pcr->ic_version = pcr->ops->get_ic_version(pcr);
    + if (pcr->ic_version == IC_VER_C) {
    + pcr->sd_pull_ctl_enable_tbl =
    + rts5229_sd_pull_ctl_enable_tbl2;
    + pcr->sd_pull_ctl_disable_tbl =
    + rts5229_sd_pull_ctl_disable_tbl2;
    + } else {
    + pcr->sd_pull_ctl_enable_tbl =
    + rts5229_sd_pull_ctl_enable_tbl1;
    + pcr->sd_pull_ctl_disable_tbl =
    + rts5229_sd_pull_ctl_disable_tbl1;
    + }
    +
    + break;
    + }
    +
    + dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
    + PCI_PID(pcr), pcr->ic_version);
    +
    + pcr->slots = kzalloc(sizeof(struct rtsx_slot) * pcr->num_slots,
    + GFP_KERNEL);
    + if (!pcr->slots)
    + return -ENOMEM;
    +
    + pcr->state = PDEV_STAT_IDLE;
    + err = rtsx_pci_init_hw(pcr);
    + if (err < 0) {
    + kfree(pcr->slots);
    + return err;
    + }
    +
    + irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
    + /* Clear interrupt flag */
    + rtsx_pci_writel(pcr, RTSX_BIPR, irq_status);
    + if (irq_status & SD_EXIST)
    + pcr->need_reset |= SD_EXIST;
    +
    + if (pcr->need_reset)
    + queue_delayed_work(workqueue, &pcr->carddet_work, 0);
    +
    + return 0;
    +}
    +
    +static int __devinit rtsx_pci_probe(struct pci_dev *pcidev,
    + const struct pci_device_id *id)
    +{
    + struct rtsx_pcr *pcr;
    + u32 base, len;
    + int ret;
    +
    + dev_dbg(&(pcidev->dev),
    + ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
    + pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
    + (int)pcidev->revision);
    +
    + ret = pci_enable_device(pcidev);
    + if (ret)
    + return ret;
    +
    + ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCR);
    + if (ret)
    + goto disable;
    +
    + pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
    + if (!pcr) {
    + ret = -ENOMEM;
    + goto release_pci;
    + }
    +
    + if (!idr_pre_get(&rtsx_pci_idr, GFP_KERNEL)) {
    + ret = -ENOMEM;
    + goto free_pcr;
    + }
    +
    + spin_lock(&rtsx_pci_lock);
    + ret = idr_get_new(&rtsx_pci_idr, pcr, &pcr->id);
    + spin_unlock(&rtsx_pci_lock);
    + if (ret)
    + goto free_pcr;
    +
    + pcr->pci = pcidev;
    + dev_set_drvdata(&pcidev->dev, pcr);
    +
    + len = pci_resource_len(pcidev, 0);
    + base = pci_resource_start(pcidev, 0);
    + pcr->remap_addr = ioremap_nocache(base, len);
    + if (!pcr->remap_addr) {
    + ret = -ENOMEM;
    + goto free_host;
    + }
    +
    + pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
    + RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
    + GFP_KERNEL);
    + if (pcr->rtsx_resv_buf == NULL) {
    + ret = -ENXIO;
    + goto unmap;
    + }
    + pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
    + pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
    + pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
    + pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
    +
    + pcr->need_reset = 0;
    + pcr->need_release = 0;
    + INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
    + INIT_WORK(&pcr->idle_work, rtsx_pci_idle_work);
    + init_timer(&pcr->idle_timer);
    +
    + pcr->msi_en = msi_en;
    + if (pcr->msi_en) {
    + ret = pci_enable_msi(pcidev);
    + if (ret < 0)
    + pcr->msi_en = false;
    + }
    +
    + ret = rtsx_pci_acquire_irq(pcr);
    + if (ret < 0)
    + goto free_dma;
    +
    + pci_set_master(pcidev);
    + synchronize_irq(pcr->irq);
    +
    + ret = rtsx_pci_init_chip(pcr);
    + if (ret < 0)
    + goto disable_irq;
    +
    + pcr->idle_timer.expires = jiffies + msecs_to_jiffies(200);
    + pcr->idle_timer.data = (unsigned long)pcr;
    + pcr->idle_timer.function = rtsx_pci_enter_idle;
    + add_timer(&pcr->idle_timer);
    +
    + return 0;
    +
    +disable_irq:
    + free_irq(pcr->irq, (void *)pcr);
    +free_dma:
    + dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
    + pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
    +unmap:
    + iounmap(pcr->remap_addr);
    +free_host:
    + dev_set_drvdata(&pcidev->dev, NULL);
    +free_pcr:
    + kfree(pcr);
    +release_pci:
    + pci_release_regions(pcidev);
    +disable:
    + pci_disable_device(pcidev);
    +
    + return ret;
    +}
    +
    +static void __devexit rtsx_pci_remove(struct pci_dev *pcidev)
    +{
    + struct rtsx_pcr *pcr = pci_get_drvdata(pcidev);
    + int i;
    +
    + pcr->remove_pci = true;
    +
    + flush_workqueue(workqueue);
    + cancel_delayed_work(&pcr->carddet_work);
    + del_timer_sync(&pcr->idle_timer);
    +
    + for (i = 0; i < pcr->num_slots; i++) {
    + if (pcr->slots[i].p_dev) {
    + platform_device_unregister(pcr->slots[i].p_dev);
    + pcr->slots[i].p_dev = NULL;
    + }
    + }
    +
    + dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
    + pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
    + free_irq(pcr->irq, (void *)pcr);
    + if (pcr->msi_en)
    + pci_disable_msi(pcr->pci);
    + iounmap(pcr->remap_addr);
    +
    + dev_set_drvdata(&pcidev->dev, NULL);
    + pci_release_regions(pcidev);
    + pci_disable_device(pcidev);
    +
    + spin_lock(&rtsx_pci_lock);
    + idr_remove(&rtsx_pci_idr, pcr->id);
    + spin_unlock(&rtsx_pci_lock);
    +
    + kfree(pcr->slots);
    + kfree(pcr);
    +
    + dev_dbg(&(pcidev->dev),
    + ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
    + pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
    +}
    +
    +#ifdef CONFIG_PM
    +
    +static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
    +{
    + struct rtsx_pcr *pcr;
    + int ret = 0;
    +
    + pcr = pci_get_drvdata(pcidev);
    +
    + pci_save_state(pcidev);
    + pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
    + pci_disable_device(pcidev);
    + pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
    +
    + return ret;
    +}
    +
    +static int rtsx_pci_resume(struct pci_dev *pcidev)
    +{
    + struct rtsx_pcr *pcr;
    + int ret = 0;
    +
    + pcr = pci_get_drvdata(pcidev);
    +
    + pci_set_power_state(pcidev, PCI_D0);
    + pci_restore_state(pcidev);
    + ret = pci_enable_device(pcidev);
    + if (ret)
    + return ret;
    +
    + return ret;
    +}
    +
    +#else /* CONFIG_PM */
    +
    +#define rtsx_pci_suspend NULL
    +#define rtsx_pci_resume NULL
    +
    +#endif /* CONFIG_PM */
    +
    +static struct pci_driver rtsx_pci_driver = {
    + .name = DRV_NAME_RTSX_PCR,
    + .id_table = rtsx_pci_ids,
    + .probe = rtsx_pci_probe,
    + .remove = __devexit_p(rtsx_pci_remove),
    + .suspend = rtsx_pci_suspend,
    + .resume = rtsx_pci_resume,
    +};
    +
    +static int __init rtsx_pci_drv_init(void)
    +{
    + workqueue = create_freezable_workqueue("rtsx_pci_wq");
    + if (!workqueue)
    + return -ENOMEM;
    +
    + return pci_register_driver(&rtsx_pci_driver);
    +}
    +
    +static void __exit rtsx_pci_drv_exit(void)
    +{
    + pci_unregister_driver(&rtsx_pci_driver);
    + destroy_workqueue(workqueue);
    +}
    +
    +module_init(rtsx_pci_drv_init);
    +module_exit(rtsx_pci_drv_exit);
    +
    +MODULE_LICENSE("GPL");
    +MODULE_AUTHOR("Realtek Corp.");
    +MODULE_DESCRIPTION("Realtek PCI-E Card Reader Adapter Driver");
    diff --git a/drivers/mfd/rtsx_pcr.h b/drivers/mfd/rtsx_pcr.h
    new file mode 100644
    index 0000000..8fbc471
    --- /dev/null
    +++ b/drivers/mfd/rtsx_pcr.h
    @@ -0,0 +1,31 @@
    +/* Driver for Realtek PCI-Express card reader
    + *
    + * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
    + *
    + * This program is free software; you can redistribute it and/or modify it
    + * under the terms of the GNU General Public License as published by the
    + * Free Software Foundation; either version 2, or (at your option) any
    + * later version.
    + *
    + * This program is distributed in the hope that it will be useful, but
    + * WITHOUT ANY WARRANTY; without even the implied warranty of
    + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
    + * General Public License for more details.
    + *
    + * You should have received a copy of the GNU General Public License along
    + * with this program; if not, see <http://www.gnu.org/licenses/>.
    + *
    + * Author:
    + * Wei WANG <wei_wang@realsil.com.cn>
    + * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
    + */
    +
    +#ifndef __RTSX_PCR_H
    +#define __RTSX_PCR_H
    +
    +#include <linux/mfd/rtsx_pci.h>
    +
    +extern const struct pcr_ops rts5209_pcr_ops;
    +extern const struct pcr_ops rts5229_pcr_ops;
    +
    +#endif
    diff --git a/include/linux/mfd/rtsx_common.h b/include/linux/mfd/rtsx_common.h
    new file mode 100644
    index 0000000..b200efc
    --- /dev/null
    +++ b/include/linux/mfd/rtsx_common.h
    @@ -0,0 +1,47 @@
    +/* Driver for Realtek driver-based card reader
    + *
    + * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
    + *
    + * This program is free software; you can redistribute it and/or modify it
    + * under the terms of the GNU General Public License as published by the
    + * Free Software Foundation; either version 2, or (at your option) any
    + * later version.
    + *
    + * This program is distributed in the hope that it will be useful, but
    + * WITHOUT ANY WARRANTY; without even the implied warranty of
    + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
    + * General Public License for more details.
    + *
    + * You should have received a copy of the GNU General Public License along
    + * with this program; if not, see <http://www.gnu.org/licenses/>.
    + *
    + * Author:
    + * Wei WANG <wei_wang@realsil.com.cn>
    + * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
    + */
    +
    +#ifndef __RTSX_COMMON_H
    +#define __RTSX_COMMON_H
    +
    +#define DRV_NAME_RTSX_PCR "rtsx_pcr"
    +#define DRV_NAME_RTSX_PCI_SDMMC "rtsx_pci_sdmmc"
    +
    +#define RTSX_REG_PAIR(addr, val) (((u32)(addr) << 16) | (u8)(val))
    +
    +#define RTSX_SSC_DEPTH_4M 0x01
    +#define RTSX_SSC_DEPTH_2M 0x02
    +#define RTSX_SSC_DEPTH_1M 0x03
    +#define RTSX_SSC_DEPTH_500K 0x04
    +#define RTSX_SSC_DEPTH_250K 0x05
    +
    +#define RTSX_SD_SLOT 0
    +#define RTSX_MS_SLOT 1
    +#define RTSX_XD_SLOT 2
    +
    +struct platform_device;
    +
    +struct rtsx_slot {
    + struct platform_device *p_dev;
    +};
    +
    +#endif
    diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
    new file mode 100644
    index 0000000..b91ca83
    --- /dev/null
    +++ b/include/linux/mfd/rtsx_pci.h
    @@ -0,0 +1,692 @@
    +/* Driver for Realtek PCI-Express card reader
    + *
    + * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
    + *
    + * This program is free software; you can redistribute it and/or modify it
    + * under the terms of the GNU General Public License as published by the
    + * Free Software Foundation; either version 2, or (at your option) any
    + * later version.
    + *
    + * This program is distributed in the hope that it will be useful, but
    + * WITHOUT ANY WARRANTY; without even the implied warranty of
    + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
    + * General Public License for more details.
    + *
    + * You should have received a copy of the GNU General Public License along
    + * with this program; if not, see <http://www.gnu.org/licenses/>.
    + *
    + * Author:
    + * Wei WANG <wei_wang@realsil.com.cn>
    + * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
    + */
    +
    +#ifndef __RTSX_PCI_H
    +#define __RTSX_PCI_H
    +
    +#include <linux/sched.h>
    +#include <linux/pci.h>
    +
    +#include "rtsx_common.h"
    +
    +#define MAX_RW_REG_CNT 1024
    +
    +#define RTSX_MAX_BLOCK_COUNT 65536
    +#define RTSX_MAX_BLOCK_LENGTH 2048
    +
    +/* PCI Operation Register Address */
    +#define RTSX_HCBAR 0x00
    +#define RTSX_HCBCTLR 0x04
    +#define RTSX_HDBAR 0x08
    +#define RTSX_HDBCTLR 0x0C
    +#define RTSX_HAIMR 0x10
    +#define RTSX_BIPR 0x14
    +#define RTSX_BIER 0x18
    +
    +/* Host command buffer control register */
    +#define STOP_CMD (0x01 << 28)
    +
    +/* Host data buffer control register */
    +#define SDMA_MODE 0x00
    +#define ADMA_MODE (0x02 << 26)
    +#define STOP_DMA (0x01 << 28)
    +#define TRIG_DMA (0x01 << 31)
    +
    +/* Bus interrupt pending register */
    +#define CMD_DONE_INT (1 << 31)
    +#define DATA_DONE_INT (1 << 30)
    +#define TRANS_OK_INT (1 << 29)
    +#define TRANS_FAIL_INT (1 << 28)
    +#define XD_INT (1 << 27)
    +#define MS_INT (1 << 26)
    +#define SD_INT (1 << 25)
    +#define GPIO0_INT (1 << 24)
    +#define OC_INT (1 << 23)
    +#define SD_WRITE_PROTECT (1 << 19)
    +#define XD_EXIST (1 << 18)
    +#define MS_EXIST (1 << 17)
    +#define SD_EXIST (1 << 16)
    +#define DELINK_INT GPIO0_INT
    +#define MS_OC_INT (1 << 23)
    +#define SD_OC_INT (1 << 22)
    +
    +#define CARD_INT (XD_INT | MS_INT | SD_INT)
    +#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
    +#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
    + CARD_INT | GPIO0_INT | OC_INT)
    +
    +#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
    +
    +/* Bus interrupt enable register */
    +#define CMD_DONE_INT_EN (1 << 31)
    +#define DATA_DONE_INT_EN (1 << 30)
    +#define TRANS_OK_INT_EN (1 << 29)
    +#define TRANS_FAIL_INT_EN (1 << 28)
    +#define XD_INT_EN (1 << 27)
    +#define MS_INT_EN (1 << 26)
    +#define SD_INT_EN (1 << 25)
    +#define GPIO0_INT_EN (1 << 24)
    +#define OC_INT_EN (1 << 23)
    +#define DELINK_INT_EN GPIO0_INT_EN
    +#define MS_OC_INT_EN (1 << 23)
    +#define SD_OC_INT_EN (1 << 22)
    +
    +#define READ_REG_CMD 0
    +#define WRITE_REG_CMD 1
    +#define CHECK_REG_CMD 2
    +
    +/*
    + * macros for easy use
    + */
    +#define rtsx_pci_writel(pcr, reg, value) \
    + iowrite32(value, (pcr)->remap_addr + reg)
    +#define rtsx_pci_readl(pcr, reg) \
    + ioread32((pcr)->remap_addr + reg)
    +#define rtsx_pci_writew(pcr, reg, value) \
    + iowrite16(value, (pcr)->remap_addr + reg)
    +#define rtsx_pci_readw(pcr, reg) \
    + ioread16((pcr)->remap_addr + reg)
    +#define rtsx_pci_writeb(pcr, reg, value) \
    + iowrite8(value, (pcr)->remap_addr + reg)
    +#define rtsx_pci_readb(pcr, reg) \
    + ioread8((pcr)->remap_addr + reg)
    +
    +#define rtsx_pci_read_config_byte(pcr, where, val) \
    + pci_read_config_byte((pcr)->pci, where, val)
    +
    +#define rtsx_pci_write_config_byte(pcr, where, val) \
    + pci_write_config_byte((pcr)->pci, where, val)
    +
    +#define rtsx_pci_read_config_dword(pcr, where, val) \
    + pci_read_config_dword((pcr)->pci, where, val)
    +
    +#define rtsx_pci_write_config_dword(pcr, where, val) \
    + pci_write_config_dword((pcr)->pci, where, val)
    +
    +#define STATE_TRANS_NONE 0
    +#define STATE_TRANS_CMD 1
    +#define STATE_TRANS_BUF 2
    +#define STATE_TRANS_SG 3
    +
    +#define TRANS_NOT_READY 0
    +#define TRANS_RESULT_OK 1
    +#define TRANS_RESULT_FAIL 2
    +#define TRANS_NO_DEVICE 3
    +
    +#define RTSX_RESV_BUF_LEN 4096
    +#define HOST_CMDS_BUF_LEN 1024
    +#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
    +
    +#define HOST_TO_DEVICE 0
    +#define DEVICE_TO_HOST 1
    +
    +#define MAX_PHASE 31
    +#define RX_TUNING_CNT 3
    +
    +/* SG descriptor */
    +#define SG_INT 0x04
    +#define SG_END 0x02
    +#define SG_VALID 0x01
    +
    +#define SG_NO_OP 0x00
    +#define SG_TRANS_DATA (0x02 << 4)
    +#define SG_LINK_DESC (0x03 << 4)
    +
    +/* SD bank voltage */
    +#define SD_IO_3V3 0
    +#define SD_IO_1V8 1
    +
    +
    +/* Card Clock Enable Register */
    +#define SD_CLK_EN 0x04
    +
    +/* Card Select Register */
    +#define SD_MOD_SEL 2
    +
    +/* Card Output Enable Register */
    +#define SD_OUTPUT_EN 0x04
    +
    +/* CARD_SHARE_MODE */
    +#define CARD_SHARE_MASK 0x0F
    +#define CARD_SHARE_MULTI_LUN 0x00
    +#define CARD_SHARE_NORMAL 0x00
    +#define CARD_SHARE_48_SD 0x04
    +/* CARD_SHARE_MODE for barossa */
    +#define CARD_SHARE_BAROSSA_SD 0x01
    +
    +/* SD30_DRIVE_SEL */
    +#define DRIVER_TYPE_A 0x05
    +#define DRIVER_TYPE_B 0x03
    +#define DRIVER_TYPE_C 0x02
    +#define DRIVER_TYPE_D 0x01
    +
    +/* FPDCTL */
    +#define SSC_POWER_DOWN 0x01
    +#define SD_OC_POWER_DOWN 0x02
    +#define ALL_POWER_DOWN 0x07
    +#define OC_POWER_DOWN 0x06
    +
    +/* CLK_CTL */
    +#define CHANGE_CLK 0x01
    +
    +/* SD_STAT1 */
    +#define SD_CRC7_ERR 0x80
    +#define SD_CRC16_ERR 0x40
    +#define SD_CRC_WRITE_ERR 0x20
    +#define SD_CRC_WRITE_ERR_MASK 0x1C
    +#define GET_CRC_TIME_OUT 0x02
    +#define SD_TUNING_COMPARE_ERR 0x01
    +
    +/* SD_STAT2 */
    +#define SD_RSP_80CLK_TIMEOUT 0x01
    +
    +/* SD_BUS_STAT */
    +#define SD_CLK_TOGGLE_EN 0x80
    +#define SD_CLK_FORCE_STOP 0x40
    +#define SD_DAT3_STATUS 0x10
    +#define SD_DAT2_STATUS 0x08
    +#define SD_DAT1_STATUS 0x04
    +#define SD_DAT0_STATUS 0x02
    +#define SD_CMD_STATUS 0x01
    +
    +/* SD_PAD_CTL */
    +#define SD_IO_USING_1V8 0x80
    +#define SD_IO_USING_3V3 0x7F
    +#define TYPE_A_DRIVING 0x00
    +#define TYPE_B_DRIVING 0x01
    +#define TYPE_C_DRIVING 0x02
    +#define TYPE_D_DRIVING 0x03
    +
    +/* SD_SAMPLE_POINT_CTL */
    +#define DDR_FIX_RX_DAT 0x00
    +#define DDR_VAR_RX_DAT 0x80
    +#define DDR_FIX_RX_DAT_EDGE 0x00
    +#define DDR_FIX_RX_DAT_14_DELAY 0x40
    +#define DDR_FIX_RX_CMD 0x00
    +#define DDR_VAR_RX_CMD 0x20
    +#define DDR_FIX_RX_CMD_POS_EDGE 0x00
    +#define DDR_FIX_RX_CMD_14_DELAY 0x10
    +#define SD20_RX_POS_EDGE 0x00
    +#define SD20_RX_14_DELAY 0x08
    +#define SD20_RX_SEL_MASK 0x08
    +
    +/* SD_PUSH_POINT_CTL */
    +#define DDR_FIX_TX_CMD_DAT 0x00
    +#define DDR_VAR_TX_CMD_DAT 0x80
    +#define DDR_FIX_TX_DAT_14_TSU 0x00
    +#define DDR_FIX_TX_DAT_12_TSU 0x40
    +#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
    +#define DDR_FIX_TX_CMD_14_AHEAD 0x20
    +#define SD20_TX_NEG_EDGE 0x00
    +#define SD20_TX_14_AHEAD 0x10
    +#define SD20_TX_SEL_MASK 0x10
    +#define DDR_VAR_SDCLK_POL_SWAP 0x01
    +
    +/* SD_TRANSFER */
    +#define SD_TRANSFER_START 0x80
    +#define SD_TRANSFER_END 0x40
    +#define SD_STAT_IDLE 0x20
    +#define SD_TRANSFER_ERR 0x10
    +/* SD Transfer Mode definition */
    +#define SD_TM_NORMAL_WRITE 0x00
    +#define SD_TM_AUTO_WRITE_3 0x01
    +#define SD_TM_AUTO_WRITE_4 0x02
    +#define SD_TM_AUTO_READ_3 0x05
    +#define SD_TM_AUTO_READ_4 0x06
    +#define SD_TM_CMD_RSP 0x08
    +#define SD_TM_AUTO_WRITE_1 0x09
    +#define SD_TM_AUTO_WRITE_2 0x0A
    +#define SD_TM_NORMAL_READ 0x0C
    +#define SD_TM_AUTO_READ_1 0x0D
    +#define SD_TM_AUTO_READ_2 0x0E
    +#define SD_TM_AUTO_TUNING 0x0F
    +
    +/* SD_VPTX_CTL / SD_VPRX_CTL */
    +#define PHASE_CHANGE 0x80
    +#define PHASE_NOT_RESET 0x40
    +
    +/* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
    +#define DCMPS_CHANGE 0x80
    +#define DCMPS_CHANGE_DONE 0x40
    +#define DCMPS_ERROR 0x20
    +#define DCMPS_CURRENT_PHASE 0x1F
    +
    +/* SD Configure 1 Register */
    +#define SD_CLK_DIVIDE_0 0x00
    +#define SD_CLK_DIVIDE_256 0xC0
    +#define SD_CLK_DIVIDE_128 0x80
    +#define SD_BUS_WIDTH_1BIT 0x00
    +#define SD_BUS_WIDTH_4BIT 0x01
    +#define SD_BUS_WIDTH_8BIT 0x02
    +#define SD_ASYNC_FIFO_NOT_RST 0x10
    +#define SD_20_MODE 0x00
    +#define SD_DDR_MODE 0x04
    +#define SD_30_MODE 0x08
    +
    +#define SD_CLK_DIVIDE_MASK 0xC0
    +
    +/* SD_CMD_STATE */
    +#define SD_CMD_IDLE 0x80
    +
    +/* SD_DATA_STATE */
    +#define SD_DATA_IDLE 0x80
    +
    +/* DCM_DRP_CTL */
    +#define DCM_RESET 0x08
    +#define DCM_LOCKED 0x04
    +#define DCM_208M 0x00
    +#define DCM_TX 0x01
    +#define DCM_RX 0x02
    +
    +/* DCM_DRP_TRIG */
    +#define DRP_START 0x80
    +#define DRP_DONE 0x40
    +
    +/* DCM_DRP_CFG */
    +#define DRP_WRITE 0x80
    +#define DRP_READ 0x00
    +#define DCM_WRITE_ADDRESS_50 0x50
    +#define DCM_WRITE_ADDRESS_51 0x51
    +#define DCM_READ_ADDRESS_00 0x00
    +#define DCM_READ_ADDRESS_51 0x51
    +
    +/* IRQSTAT0 */
    +#define DMA_DONE_INT 0x80
    +#define SUSPEND_INT 0x40
    +#define LINK_RDY_INT 0x20
    +#define LINK_DOWN_INT 0x10
    +
    +/* DMACTL */
    +#define DMA_RST 0x80
    +#define DMA_BUSY 0x04
    +#define DMA_DIR_TO_CARD 0x00
    +#define DMA_DIR_FROM_CARD 0x02
    +#define DMA_EN 0x01
    +#define DMA_128 (0 << 4)
    +#define DMA_256 (1 << 4)
    +#define DMA_512 (2 << 4)
    +#define DMA_1024 (3 << 4)
    +#define DMA_PACK_SIZE_MASK 0x30
    +
    +/* SSC_CTL1 */
    +#define SSC_RSTB 0x80
    +#define SSC_8X_EN 0x40
    +#define SSC_FIX_FRAC 0x20
    +#define SSC_SEL_1M 0x00
    +#define SSC_SEL_2M 0x08
    +#define SSC_SEL_4M 0x10
    +#define SSC_SEL_8M 0x18
    +
    +/* SSC_CTL2 */
    +#define SSC_DEPTH_MASK 0x07
    +#define SSC_DEPTH_DISALBE 0x00
    +#define SSC_DEPTH_4M 0x01
    +#define SSC_DEPTH_2M 0x02
    +#define SSC_DEPTH_1M 0x03
    +#define SSC_DEPTH_500K 0x04
    +#define SSC_DEPTH_250K 0x05
    +
    +/* System Clock Control Register */
    +#define CLK_LOW_FREQ 0x01
    +
    +/* System Clock Divider Register */
    +#define CLK_DIV_1 0x01
    +#define CLK_DIV_2 0x02
    +#define CLK_DIV_4 0x03
    +#define CLK_DIV_8 0x04
    +
    +/* SD Configure 2 Register */
    +#define SD_CALCULATE_CRC7 0x00
    +#define SD_NO_CALCULATE_CRC7 0x80
    +#define SD_CHECK_CRC16 0x00
    +#define SD_NO_CHECK_CRC16 0x40
    +#define SD_NO_CHECK_WAIT_CRC_TO 0x20
    +#define SD_WAIT_BUSY_END 0x08
    +#define SD_NO_WAIT_BUSY_END 0x00
    +#define SD_CHECK_CRC7 0x00
    +#define SD_NO_CHECK_CRC7 0x04
    +#define SD_RSP_LEN_0 0x00
    +#define SD_RSP_LEN_6 0x01
    +#define SD_RSP_LEN_17 0x02
    +/* SD/MMC Response Type Definition */
    +#define SD_RSP_TYPE_R0 0x04
    +#define SD_RSP_TYPE_R1 0x01
    +#define SD_RSP_TYPE_R1b 0x09
    +#define SD_RSP_TYPE_R2 0x02
    +#define SD_RSP_TYPE_R3 0x05
    +#define SD_RSP_TYPE_R4 0x05
    +#define SD_RSP_TYPE_R5 0x01
    +#define SD_RSP_TYPE_R6 0x01
    +#define SD_RSP_TYPE_R7 0x01
    +
    +/* SD_CONFIURE3 */
    +#define SD_RSP_80CLK_TIMEOUT_EN 0x01
    +
    +/* Card Transfer Reset Register */
    +#define SPI_STOP 0x01
    +#define XD_STOP 0x02
    +#define SD_STOP 0x04
    +#define MS_STOP 0x08
    +#define SPI_CLR_ERR 0x10
    +#define XD_CLR_ERR 0x20
    +#define SD_CLR_ERR 0x40
    +#define MS_CLR_ERR 0x80
    +
    +/* Card Data Source Register */
    +#define PINGPONG_BUFFER 0x01
    +#define RING_BUFFER 0x00
    +
    +/* Card Power Control Register */
    +#define PMOS_STRG_MASK 0x10
    +#define PMOS_STRG_800mA 0x10
    +#define PMOS_STRG_400mA 0x00
    +#define SD_POWER_OFF 0x03
    +#define SD_PARTIAL_POWER_ON 0x01
    +#define SD_POWER_ON 0x00
    +#define SD_POWER_MASK 0x03
    +
    +/* PWR_GATE_CTRL */
    +#define PWR_GATE_EN 0x01
    +#define LDO3318_PWR_MASK 0x06
    +#define LDO_ON 0x00
    +#define LDO_SUSPEND 0x04
    +#define LDO_OFF 0x06
    +
    +/* CARD_CLK_SOURCE */
    +#define CRC_FIX_CLK (0x00 << 0)
    +#define CRC_VAR_CLK0 (0x01 << 0)
    +#define CRC_VAR_CLK1 (0x02 << 0)
    +#define SD30_FIX_CLK (0x00 << 2)
    +#define SD30_VAR_CLK0 (0x01 << 2)
    +#define SD30_VAR_CLK1 (0x02 << 2)
    +#define SAMPLE_FIX_CLK (0x00 << 4)
    +#define SAMPLE_VAR_CLK0 (0x01 << 4)
    +#define SAMPLE_VAR_CLK1 (0x02 << 4)
    +
    +#define SD_CFG1 0xFDA0
    +#define SD_CFG2 0xFDA1
    +#define SD_CFG3 0xFDA2
    +#define SD_STAT1 0xFDA3
    +#define SD_STAT2 0xFDA4
    +#define SD_BUS_STAT 0xFDA5
    +#define SD_PAD_CTL 0xFDA6
    +#define SD_SAMPLE_POINT_CTL 0xFDA7
    +#define SD_PUSH_POINT_CTL 0xFDA8
    +#define SD_CMD0 0xFDA9
    +#define SD_CMD1 0xFDAA
    +#define SD_CMD2 0xFDAB
    +#define SD_CMD3 0xFDAC
    +#define SD_CMD4 0xFDAD
    +#define SD_CMD5 0xFDAE
    +#define SD_BYTE_CNT_L 0xFDAF
    +#define SD_BYTE_CNT_H 0xFDB0
    +#define SD_BLOCK_CNT_L 0xFDB1
    +#define SD_BLOCK_CNT_H 0xFDB2
    +#define SD_TRANSFER 0xFDB3
    +#define SD_CMD_STATE 0xFDB5
    +#define SD_DATA_STATE 0xFDB6
    +
    +#define SRCTL 0xFC13
    +
    +#define DCM_DRP_CTL 0xFC23
    +#define DCM_DRP_TRIG 0xFC24
    +#define DCM_DRP_CFG 0xFC25
    +#define DCM_DRP_WR_DATA_L 0xFC26
    +#define DCM_DRP_WR_DATA_H 0xFC27
    +#define DCM_DRP_RD_DATA_L 0xFC28
    +#define DCM_DRP_RD_DATA_H 0xFC29
    +#define SD_VPCLK0_CTL 0xFC2A
    +#define SD_VPCLK1_CTL 0xFC2B
    +#define SD_DCMPS0_CTL 0xFC2C
    +#define SD_DCMPS1_CTL 0xFC2D
    +#define SD_VPTX_CTL SD_VPCLK0_CTL
    +#define SD_VPRX_CTL SD_VPCLK1_CTL
    +#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
    +#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
    +#define CARD_CLK_SOURCE 0xFC2E
    +
    +#define CARD_PWR_CTL 0xFD50
    +#define CARD_CLK_SWITCH 0xFD51
    +#define CARD_SHARE_MODE 0xFD52
    +#define CARD_DRIVE_SEL 0xFD53
    +#define CARD_STOP 0xFD54
    +#define CARD_OE 0xFD55
    +#define CARD_AUTO_BLINK 0xFD56
    +#define CARD_GPIO_DIR 0xFD57
    +#define CARD_GPIO 0xFD58
    +
    +#define CARD_DATA_SOURCE 0xFD5B
    +#define CARD_SELECT 0xFD5C
    +#define SD30_DRIVE_SEL 0xFD5E
    +
    +#define CARD_CLK_EN 0xFD69
    +
    +#define SDIO_CTRL 0xFD6B
    +
    +#define FPDCTL 0xFC00
    +#define PDINFO 0xFC01
    +
    +#define CLK_CTL 0xFC02
    +#define CLK_DIV 0xFC03
    +#define CLK_SEL 0xFC04
    +
    +#define SSC_DIV_N_0 0xFC0F
    +#define SSC_DIV_N_1 0xFC10
    +#define SSC_CTL1 0xFC11
    +#define SSC_CTL2 0xFC12
    +
    +#define RCCTL 0xFC14
    +
    +#define FPGA_PULL_CTL 0xFC1D
    +
    +#define CARD_PULL_CTL1 0xFD60
    +#define CARD_PULL_CTL2 0xFD61
    +#define CARD_PULL_CTL3 0xFD62
    +#define CARD_PULL_CTL4 0xFD63
    +#define CARD_PULL_CTL5 0xFD64
    +#define CARD_PULL_CTL6 0xFD65
    +
    +/* PCI Express Related Registers */
    +#define IRQEN0 0xFE20
    +#define IRQSTAT0 0xFE21
    +#define IRQEN1 0xFE22
    +#define IRQSTAT1 0xFE23
    +#define TLPRIEN 0xFE24
    +#define TLPRISTAT 0xFE25
    +#define TLPTIEN 0xFE26
    +#define TLPTISTAT 0xFE27
    +#define DMATC0 0xFE28
    +#define DMATC1 0xFE29
    +#define DMATC2 0xFE2A
    +#define DMATC3 0xFE2B
    +#define DMACTL 0xFE2C
    +#define BCTL 0xFE2D
    +#define RBBC0 0xFE2E
    +#define RBBC1 0xFE2F
    +#define RBDAT 0xFE30
    +#define RBCTL 0xFE34
    +#define CFGADDR0 0xFE35
    +#define CFGADDR1 0xFE36
    +#define CFGDATA0 0xFE37
    +#define CFGDATA1 0xFE38
    +#define CFGDATA2 0xFE39
    +#define CFGDATA3 0xFE3A
    +#define CFGRWCTL 0xFE3B
    +#define PHYRWCTL 0xFE3C
    +#define PHYDATA0 0xFE3D
    +#define PHYDATA1 0xFE3E
    +#define PHYADDR 0xFE3F
    +#define MSGRXDATA0 0xFE40
    +#define MSGRXDATA1 0xFE41
    +#define MSGRXDATA2 0xFE42
    +#define MSGRXDATA3 0xFE43
    +#define MSGTXDATA0 0xFE44
    +#define MSGTXDATA1 0xFE45
    +#define MSGTXDATA2 0xFE46
    +#define MSGTXDATA3 0xFE47
    +#define MSGTXCTL 0xFE48
    +#define PETXCFG 0xFE49
    +
    +#define CDRESUMECTL 0xFE52
    +#define WAKE_SEL_CTL 0xFE54
    +#define PME_FORCE_CTL 0xFE56
    +#define ASPM_FORCE_CTL 0xFE57
    +#define PM_CLK_FORCE_CTL 0xFE58
    +#define PERST_GLITCH_WIDTH 0xFE5C
    +#define CHANGE_LINK_STATE 0xFE5B
    +#define RESET_LOAD_REG 0xFE5E
    +#define EFUSE_CONTENT 0xFE5F
    +#define HOST_SLEEP_STATE 0xFE60
    +#define MAIN_PWR_OFF_CTL 0xFE70 /* RTS5208 */
    +#define SDIO_CFG 0xFE70 /* RTS5209 */
    +
    +#define NFTS_TX_CTRL 0xFE72
    +
    +#define PWR_GATE_CTRL 0xFE75
    +#define PWD_SUSPEND_EN 0xFE76
    +
    +/* Memory mapping */
    +#define SRAM_BASE 0xE600
    +#define RBUF_BASE 0xF400
    +#define PPBUF_BASE1 0xF800
    +#define PPBUF_BASE2 0xFA00
    +#define IMAGE_FLAG_ADDR0 0xCE80
    +#define IMAGE_FLAG_ADDR1 0xCE81
    +
    +#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
    +
    +struct reg_val {
    + /* Enable signal for regulator3318 */
    + u8 ldo_pwr_on;
    + u8 ldo_pwr_off;
    + u8 ldo_pwr_suspend;
    +};
    +
    +struct rtsx_pcr;
    +
    +struct pcr_ops {
    + u8 (*get_ic_version)(struct rtsx_pcr *pcr);
    + int (*extra_init_hw)(struct rtsx_pcr *pcr);
    + int (*optimize_phy)(struct rtsx_pcr *pcr);
    + int (*turn_on_led)(struct rtsx_pcr *pcr);
    + int (*turn_off_led)(struct rtsx_pcr *pcr);
    + int (*enable_auto_blink)(struct rtsx_pcr *pcr);
    + int (*disable_auto_blink)(struct rtsx_pcr *pcr);
    +};
    +
    +enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
    +
    +struct rtsx_pcr {
    + struct pci_dev *pci;
    + unsigned int id;
    +
    + /* pci resources */
    + unsigned long addr;
    + void __iomem *remap_addr;
    + int irq;
    +
    + /* host reserved buffer */
    + void *rtsx_resv_buf;
    + dma_addr_t rtsx_resv_buf_addr;
    +
    + void *host_cmds_ptr;
    + dma_addr_t host_cmds_addr;
    + int ci;
    +
    + void *host_sg_tbl_ptr;
    + dma_addr_t host_sg_tbl_addr;
    + int sgi;
    +
    + u32 int_reg;
    + char trans_result;
    + char trans_state;
    +
    + int need_reset;
    + int need_release;
    +
    + struct delayed_work carddet_work;
    + struct timer_list idle_timer;
    + struct work_struct idle_work;
    +
    + spinlock_t lock;
    + struct mutex pcr_mutex;
    + struct completion *done;
    + struct completion *finish_me;
    +
    + bool remove_pci;
    + bool msi_en;
    +
    +#define EXTRA_CAPS_SD_SDR50 (1 << 0)
    +#define EXTRA_CAPS_SD_SDR104 (1 << 1)
    +#define EXTRA_CAPS_SD_DDR50 (1 << 2)
    +#define EXTRA_CAPS_MMC_HSDDR (1 << 3)
    +#define EXTRA_CAPS_MMC_HS200 (1 << 4)
    +#define EXTRA_CAPS_MMC_8BIT (1 << 5)
    + u32 extra_caps;
    +
    +#define IC_VER_A 0
    +#define IC_VER_B 1
    +#define IC_VER_C 2
    +#define IC_VER_D 3
    + u8 ic_version;
    +
    + struct reg_val rval;
    + const u32 *sd_pull_ctl_enable_tbl;
    + const u32 *sd_pull_ctl_disable_tbl;
    +
    + const struct pcr_ops *ops;
    + enum PDEV_STAT state;
    +
    + int num_slots;
    + struct rtsx_slot *slots;
    +};
    +
    +#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
    +#define PCI_VID(pcr) ((pcr)->pci->vendor)
    +#define PCI_PID(pcr) ((pcr)->pci->device)
    +
    +void rtsx_pci_start_run(struct rtsx_pcr *pcr);
    +int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
    +int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
    +int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
    +int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
    +void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
    +void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
    + u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
    +void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
    +int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
    +int rtsx_pci_transfer_data(struct rtsx_pcr *pcr,
    + void *buf, size_t len, int use_sg, int read, int timeout);
    +int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
    +int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
    +int rtsx_pci_sd_pull_ctl_enable(struct rtsx_pcr *pcr);
    +int rtsx_pci_sd_pull_ctl_disable(struct rtsx_pcr *pcr);
    +int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
    + u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
    +void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
    +
    +static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
    +{
    + return (u8 *)(pcr->host_cmds_ptr);
    +}
    +
    +#endif
    --
    1.7.9.5


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      Last update: 2012-08-14 13:22    [W:9.498 / U:0.660 seconds]
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