lkml.org 
[lkml]   [2012]   [Jul]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[ 15/37] e1000e: Correct link check logic for 82571 serdes
    Date
    From: Greg KH <gregkh@linuxfoundation.org>

    3.4-stable review patch. If anyone has any objections, please let me know.

    ------------------

    From: Tushar Dave <tushar.n.dave@intel.com>

    commit d0efa8f23a644f7cb7d1f8e78dd9a223efa412a3 upstream.

    SYNCH bit and IV bit of RXCW register are sticky. Before examining these bits,
    RXCW should be read twice to filter out one-time false events and have correct
    values for these bits. Incorrect values of these bits in link check logic can
    cause weird link stability issues if auto-negotiation fails.

    Reported-by: Dean Nelson <dnelson@redhat.com>
    Signed-off-by: Tushar Dave <tushar.n.dave@intel.com>
    Reviewed-by: Bruce Allan <bruce.w.allan@intel.com>
    Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
    Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/net/ethernet/intel/e1000e/82571.c | 3 +++
    1 file changed, 3 insertions(+)

    --- a/drivers/net/ethernet/intel/e1000e/82571.c
    +++ b/drivers/net/ethernet/intel/e1000e/82571.c
    @@ -1553,6 +1553,9 @@ static s32 e1000_check_for_serdes_link_8
    ctrl = er32(CTRL);
    status = er32(STATUS);
    rxcw = er32(RXCW);
    + /* SYNCH bit and IV bit are sticky */
    + udelay(10);
    + rxcw = er32(RXCW);

    if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {




    \
     
     \ /
      Last update: 2012-07-18 05:01    [W:4.049 / U:1.336 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site