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    Subject[PATCH V3] perf/x86: Add Intel Nehalem-EX/Westmere-EX uncore support
    Date
    From: "Yan, Zheng" <zheng.z.yan@intel.com>

    The uncore subsystem in Nehalem-EX/Westmere-EX consists of
    7 components (U-Box, C-Box, B-Box, S-Box, R-Box, M-Box and
    W-Box). This patch is large because the way to program these
    boxes is diverse.

    Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
    ---
    Changes since v2:
    -Add code to explicit specify MSR offsets between uncore boxes
    -Add Westmere-EX support
    -Filter registers related fixes. (check if a event can use the filter function)
    -Cleanup the code for Rbox

    arch/x86/kernel/cpu/perf_event_intel_uncore.c | 1235 +++++++++++++++++++++++--
    arch/x86/kernel/cpu/perf_event_intel_uncore.h | 229 ++++-
    2 files changed, 1365 insertions(+), 99 deletions(-)

    diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
    index 19faffc..8b3ad82 100644
    --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
    +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
    @@ -26,17 +26,1133 @@ DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
    DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
    DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
    DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
    -DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
    -DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
    -DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
    -DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
    -DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
    -DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
    -DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
    -DEFINE_UNCORE_FORMAT_ATTR(filter_brand0, filter_brand0, "config1:0-7");
    -DEFINE_UNCORE_FORMAT_ATTR(filter_brand1, filter_brand1, "config1:8-15");
    -DEFINE_UNCORE_FORMAT_ATTR(filter_brand2, filter_brand2, "config1:16-23");
    -DEFINE_UNCORE_FORMAT_ATTR(filter_brand3, filter_brand3, "config1:24-31");
    +
    +static u64 uncore_msr_read_counter(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + u64 count;
    + rdmsrl(event->hw.event_base, count);
    + return count;
    +}
    +
    +/*
    + * generic get constraint function for shared match/mask registers.
    + */
    +static struct event_constraint *
    +uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
    +{
    + struct intel_uncore_extra_reg *er;
    + struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
    + struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
    + unsigned long flags;
    + bool ok = false;
    +
    + /*
    + * reg->alloc can be set due to existing state, so for fake box we
    + * need to ignore this, otherwise we might fail to allocate proper
    + * fake state for this extra reg constraint.
    + */
    + if (reg1->idx == EXTRA_REG_NONE ||
    + (!uncore_box_is_fake(box) && reg1->alloc))
    + return NULL;
    +
    + er = &box->shared_regs[reg1->idx];
    + raw_spin_lock_irqsave(&er->lock, flags);
    + if (!atomic_read(&er->ref) ||
    + (er->config1 == reg1->config && er->config2 == reg2->config)) {
    + atomic_inc(&er->ref);
    + er->config1 = reg1->config;
    + er->config2 = reg2->config;
    + ok = true;
    + }
    + raw_spin_unlock_irqrestore(&er->lock, flags);
    +
    + if (ok) {
    + if (!uncore_box_is_fake(box))
    + reg1->alloc = 1;
    + return NULL;
    + }
    +
    + return &constraint_empty;
    +}
    +
    +static void uncore_put_constraint(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct intel_uncore_extra_reg *er;
    + struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
    +
    + /*
    + * Only put constraint if extra reg was actually allocated. Also
    + * takes care of event which do not use an extra shared reg.
    + *
    + * Also, if this is a fake box we shouldn't touch any event state
    + * (reg->alloc) and we don't care about leaving inconsistent box
    + * state either since it will be thrown out.
    + */
    + if (uncore_box_is_fake(box) || !reg1->alloc)
    + return;
    +
    + er = &box->shared_regs[reg1->idx];
    + atomic_dec(&er->ref);
    + reg1->alloc = 0;
    +}
    +
    +/* Nehalem-EX/Westmere-EX uncore support */
    +#define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \
    + ((1ULL << (n)) - 1)))
    +
    +DEFINE_UNCORE_FORMAT_ATTR(event5, event, "config:1-5");
    +DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-7");
    +DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
    +DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63");
    +
    +static void nhmex_uncore_msr_init_box(struct intel_uncore_box *box)
    +{
    + wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL);
    +}
    +
    +static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box)
    +{
    + unsigned msr = uncore_msr_box_ctl(box);
    + u64 config;
    + if (msr) {
    + rdmsrl(msr, config);
    + config &= ~((1ULL << uncore_num_counters(box)) - 1);
    + /* WBox has a fixed counter */
    + if (uncore_msr_fixed_ctl(box))
    + config &= ~NHMEX_W_PMON_GLOBAL_FIXED_EN;
    + wrmsrl(msr, config);
    + }
    +}
    +
    +static void nhmex_uncore_msr_enable_box(struct intel_uncore_box *box)
    +{
    + unsigned msr = uncore_msr_box_ctl(box);
    + u64 config;
    + if (msr) {
    + rdmsrl(msr, config);
    + config |= (1ULL << uncore_num_counters(box)) - 1;
    + /* WBox has a fixed counter */
    + if (uncore_msr_fixed_ctl(box))
    + config |= NHMEX_W_PMON_GLOBAL_FIXED_EN;
    + wrmsrl(msr, config);
    + }
    +}
    +
    +static void nhmex_uncore_msr_disable_event(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + wrmsrl(event->hw.config_base, 0);
    +}
    +
    +static void nhmex_uncore_msr_enable_event(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    +
    + if (hwc->idx >= UNCORE_PMC_IDX_FIXED)
    + wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0);
    + else if (box->pmu->type->event_mask & NHMEX_PMON_CTL_EN_BIT0)
    + wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
    + else
    + wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
    +}
    +
    +#define NHMEX_UNCORE_OPS_COMMON_INIT() \
    + .init_box = nhmex_uncore_msr_init_box, \
    + .disable_box = nhmex_uncore_msr_disable_box, \
    + .enable_box = nhmex_uncore_msr_enable_box, \
    + .disable_event = nhmex_uncore_msr_disable_event, \
    + .read_counter = uncore_msr_read_counter
    +
    +static struct intel_uncore_ops nhmex_uncore_ops = {
    + NHMEX_UNCORE_OPS_COMMON_INIT(),
    + .enable_event = nhmex_uncore_msr_enable_event,
    +};
    +
    +static struct attribute *nhmex_uncore_ubox_formats_attr[] = {
    + &format_attr_event.attr,
    + &format_attr_edge.attr,
    + NULL,
    +};
    +
    +static struct attribute_group nhmex_uncore_ubox_format_group = {
    + .name = "format",
    + .attrs = nhmex_uncore_ubox_formats_attr,
    +};
    +
    +static struct intel_uncore_type nhmex_uncore_ubox = {
    + .name = "ubox",
    + .num_counters = 1,
    + .num_boxes = 1,
    + .perf_ctr_bits = 48,
    + .event_ctl = NHMEX_U_MSR_PMON_EV_SEL,
    + .perf_ctr = NHMEX_U_MSR_PMON_CTR,
    + .event_mask = NHMEX_U_PMON_RAW_EVENT_MASK,
    + .box_ctl = NHMEX_U_MSR_PMON_GLOBAL_CTL,
    + .ops = &nhmex_uncore_ops,
    + .format_group = &nhmex_uncore_ubox_format_group
    +};
    +
    +static struct attribute *nhmex_uncore_cbox_formats_attr[] = {
    + &format_attr_event.attr,
    + &format_attr_umask.attr,
    + &format_attr_edge.attr,
    + &format_attr_inv.attr,
    + &format_attr_thresh8.attr,
    + NULL,
    +};
    +
    +static struct attribute_group nhmex_uncore_cbox_format_group = {
    + .name = "format",
    + .attrs = nhmex_uncore_cbox_formats_attr,
    +};
    +
    +/* msr offset for each instance of cbox */
    +static unsigned nhmex_cbox_msr_offsets[] = {
    + 0x0, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x240, 0x2c0,
    +};
    +
    +static struct intel_uncore_type nhmex_uncore_cbox = {
    + .name = "cbox",
    + .num_counters = 6,
    + .num_boxes = 10,
    + .perf_ctr_bits = 48,
    + .event_ctl = NHMEX_C0_MSR_PMON_EV_SEL0,
    + .perf_ctr = NHMEX_C0_MSR_PMON_CTR0,
    + .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
    + .box_ctl = NHMEX_C0_MSR_PMON_GLOBAL_CTL,
    + .msr_offsets = nhmex_cbox_msr_offsets,
    + .pair_ctr_ctl = 1,
    + .ops = &nhmex_uncore_ops,
    + .format_group = &nhmex_uncore_cbox_format_group
    +};
    +
    +static struct uncore_event_desc nhmex_uncore_wbox_events[] = {
    + INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0"),
    + { /* end: all zeroes */ },
    +};
    +
    +static struct intel_uncore_type nhmex_uncore_wbox = {
    + .name = "wbox",
    + .num_counters = 4,
    + .num_boxes = 1,
    + .perf_ctr_bits = 48,
    + .event_ctl = NHMEX_W_MSR_PMON_CNT0,
    + .perf_ctr = NHMEX_W_MSR_PMON_EVT_SEL0,
    + .fixed_ctr = NHMEX_W_MSR_PMON_FIXED_CTR,
    + .fixed_ctl = NHMEX_W_MSR_PMON_FIXED_CTL,
    + .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
    + .box_ctl = NHMEX_W_MSR_GLOBAL_CTL,
    + .pair_ctr_ctl = 1,
    + .event_descs = nhmex_uncore_wbox_events,
    + .ops = &nhmex_uncore_ops,
    + .format_group = &nhmex_uncore_cbox_format_group
    +};
    +
    +static int nhmex_bbox_hw_config(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    + struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
    + struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
    + int ctr, ev_sel;
    +
    + ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >>
    + NHMEX_B_PMON_CTR_SHIFT;
    + ev_sel = (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK) >>
    + NHMEX_B_PMON_CTL_EV_SEL_SHIFT;
    +
    + /* events that do not use the match/mask registers */
    + if ((ctr == 0 && ev_sel > 0x3) || (ctr == 1 && ev_sel > 0x6) ||
    + (ctr == 2 && ev_sel != 0x4) || ctr == 3)
    + return 0;
    +
    + if (box->pmu->pmu_idx == 0)
    + reg1->reg = NHMEX_B0_MSR_MATCH;
    + else
    + reg1->reg = NHMEX_B1_MSR_MATCH;
    + reg1->idx = 0;
    + reg1->config = event->attr.config1;
    + reg2->config = event->attr.config2;
    + return 0;
    +}
    +
    +static void nhmex_bbox_msr_enable_event(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    + struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
    + struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
    +
    + if (reg1->idx != EXTRA_REG_NONE) {
    + wrmsrl(reg1->reg, reg1->config);
    + wrmsrl(reg1->reg + 1, reg2->config);
    + }
    + wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
    + (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK));
    +}
    +
    +/*
    + * The Bbox has 4 counters, but each counter monitors different events.
    + * Use bits 6-7 in the event config to select counter.
    + */
    +static struct event_constraint nhmex_uncore_bbox_constraints[] = {
    + EVENT_CONSTRAINT(0 , 1, 0xc0),
    + EVENT_CONSTRAINT(0x40, 2, 0xc0),
    + EVENT_CONSTRAINT(0x80, 4, 0xc0),
    + EVENT_CONSTRAINT(0xc0, 8, 0xc0),
    + EVENT_CONSTRAINT_END,
    +};
    +
    +static struct attribute *nhmex_uncore_bbox_formats_attr[] = {
    + &format_attr_event5.attr,
    + &format_attr_counter.attr,
    + &format_attr_match.attr,
    + &format_attr_mask.attr,
    + NULL,
    +};
    +
    +static struct attribute_group nhmex_uncore_bbox_format_group = {
    + .name = "format",
    + .attrs = nhmex_uncore_bbox_formats_attr,
    +};
    +
    +static struct intel_uncore_ops nhmex_uncore_bbox_ops = {
    + NHMEX_UNCORE_OPS_COMMON_INIT(),
    + .enable_event = nhmex_bbox_msr_enable_event,
    + .hw_config = nhmex_bbox_hw_config,
    + .get_constraint = uncore_get_constraint,
    + .put_constraint = uncore_put_constraint,
    +};
    +
    +static struct intel_uncore_type nhmex_uncore_bbox = {
    + .name = "bbox",
    + .num_counters = 4,
    + .num_boxes = 2,
    + .perf_ctr_bits = 48,
    + .event_ctl = NHMEX_B0_MSR_PMON_CTL0,
    + .perf_ctr = NHMEX_B0_MSR_PMON_CTR0,
    + .event_mask = NHMEX_B_PMON_RAW_EVENT_MASK,
    + .box_ctl = NHMEX_B0_MSR_PMON_GLOBAL_CTL,
    + .msr_offset = NHMEX_B_MSR_OFFSET,
    + .pair_ctr_ctl = 1,
    + .num_shared_regs = 1,
    + .constraints = nhmex_uncore_bbox_constraints,
    + .ops = &nhmex_uncore_bbox_ops,
    + .format_group = &nhmex_uncore_bbox_format_group
    +};
    +
    +static int nhmex_sbox_hw_config(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    + struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
    + struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
    +
    + /* only TO_R_PROG_EV event uses the match/mask register */
    + if ((hwc->config & NHMEX_PMON_CTL_EV_SEL_MASK) !=
    + NHMEX_S_EVENT_TO_R_PROG_EV)
    + return 0;
    +
    + if (box->pmu->pmu_idx == 0)
    + reg1->reg = NHMEX_S0_MSR_MM_CFG;
    + else
    + reg1->reg = NHMEX_S1_MSR_MM_CFG;
    + reg1->idx = 0;
    + reg1->config = event->attr.config1;
    + reg2->config = event->attr.config2;
    + return 0;
    +}
    +
    +static void nhmex_sbox_msr_enable_event(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    + struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
    + struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
    +
    + if (reg1->idx != EXTRA_REG_NONE) {
    + wrmsrl(reg1->reg, 0);
    + wrmsrl(reg1->reg + 1, reg1->config);
    + wrmsrl(reg1->reg + 2, reg2->config);
    + wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN);
    + }
    + wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
    +}
    +
    +static struct attribute *nhmex_uncore_sbox_formats_attr[] = {
    + &format_attr_event.attr,
    + &format_attr_umask.attr,
    + &format_attr_edge.attr,
    + &format_attr_inv.attr,
    + &format_attr_thresh8.attr,
    + &format_attr_match.attr,
    + &format_attr_mask.attr,
    + NULL,
    +};
    +
    +static struct attribute_group nhmex_uncore_sbox_format_group = {
    + .name = "format",
    + .attrs = nhmex_uncore_sbox_formats_attr,
    +};
    +
    +static struct intel_uncore_ops nhmex_uncore_sbox_ops = {
    + NHMEX_UNCORE_OPS_COMMON_INIT(),
    + .enable_event = nhmex_sbox_msr_enable_event,
    + .hw_config = nhmex_sbox_hw_config,
    + .get_constraint = uncore_get_constraint,
    + .put_constraint = uncore_put_constraint,
    +};
    +
    +static struct intel_uncore_type nhmex_uncore_sbox = {
    + .name = "sbox",
    + .num_counters = 4,
    + .num_boxes = 2,
    + .perf_ctr_bits = 48,
    + .event_ctl = NHMEX_S0_MSR_PMON_CTL0,
    + .perf_ctr = NHMEX_S0_MSR_PMON_CTR0,
    + .event_mask = NHMEX_PMON_RAW_EVENT_MASK,
    + .box_ctl = NHMEX_S0_MSR_PMON_GLOBAL_CTL,
    + .msr_offset = NHMEX_S_MSR_OFFSET,
    + .pair_ctr_ctl = 1,
    + .num_shared_regs = 1,
    + .ops = &nhmex_uncore_sbox_ops,
    + .format_group = &nhmex_uncore_sbox_format_group
    +};
    +
    +enum {
    + EXTRA_REG_NHMEX_M_FILTER,
    + EXTRA_REG_NHMEX_M_DSP,
    + EXTRA_REG_NHMEX_M_ISS,
    + EXTRA_REG_NHMEX_M_MAP,
    + EXTRA_REG_NHMEX_M_MSC_THR,
    + EXTRA_REG_NHMEX_M_PGT,
    + EXTRA_REG_NHMEX_M_PLD,
    + EXTRA_REG_NHMEX_M_ZDP_CTL_FVC,
    +};
    +
    +static struct extra_reg nhmex_uncore_mbox_extra_regs[] = {
    + MBOX_INC_SEL_EXTAR_REG(0x0, DSP),
    + MBOX_INC_SEL_EXTAR_REG(0x4, MSC_THR),
    + MBOX_INC_SEL_EXTAR_REG(0x5, MSC_THR),
    + MBOX_INC_SEL_EXTAR_REG(0x9, ISS),
    + /* event 0xa uses two extra registers */
    + MBOX_INC_SEL_EXTAR_REG(0xa, ISS),
    + MBOX_INC_SEL_EXTAR_REG(0xa, PLD),
    + MBOX_INC_SEL_EXTAR_REG(0xb, PLD),
    + /* events 0xd ~ 0x10 use the same extra register */
    + MBOX_INC_SEL_EXTAR_REG(0xd, ZDP_CTL_FVC),
    + MBOX_INC_SEL_EXTAR_REG(0xe, ZDP_CTL_FVC),
    + MBOX_INC_SEL_EXTAR_REG(0xf, ZDP_CTL_FVC),
    + MBOX_INC_SEL_EXTAR_REG(0x10, ZDP_CTL_FVC),
    + MBOX_INC_SEL_EXTAR_REG(0x16, PGT),
    + MBOX_SET_FLAG_SEL_EXTRA_REG(0x0, DSP),
    + MBOX_SET_FLAG_SEL_EXTRA_REG(0x1, ISS),
    + MBOX_SET_FLAG_SEL_EXTRA_REG(0x5, PGT),
    + MBOX_SET_FLAG_SEL_EXTRA_REG(0x6, MAP),
    + EVENT_EXTRA_END
    +};
    +
    +/* Nehalem-EX or Westmere-EX ? */
    +static bool uncore_nhmex;
    +
    +static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box,
    + int idx, u64 config)
    +{
    + struct intel_uncore_extra_reg *er;
    + unsigned long flags;
    + bool ret = false;
    + u64 mask;
    +
    + if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
    + er = &box->shared_regs[idx];
    + raw_spin_lock_irqsave(&er->lock, flags);
    + if (!atomic_read(&er->ref) || er->config1 == config) {
    + atomic_inc(&er->ref);
    + er->config1 = config;
    + ret = true;
    + }
    + raw_spin_unlock_irqrestore(&er->lock, flags);
    + return ret;
    + }
    + /*
    + * The ZDP_CTL_FVC MSR has 4 fields which are used to control
    + * events 0xd ~ 0x10. Besides these 4 fields, there are additional
    + * fields which are shared.
    + */
    + idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
    + if (WARN_ON_ONCE(idx >= 4))
    + return false;
    +
    + /* mask of the shared fields */
    + if (uncore_nhmex)
    + mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK;
    + else
    + mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK;
    + er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
    + raw_spin_lock_irqsave(&er->lock, flags);
    + /* add mask of the non-shared field if it's in use */
    + if (__BITS_VALUE(atomic_read(&er->ref), idx, 8)) {
    + if (uncore_nhmex)
    + mask |= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
    + else
    + mask |= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
    + }
    +
    + if (!atomic_read(&er->ref) || !((er->config1 ^ config) & mask)) {
    + if (uncore_nhmex)
    + mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK |
    + NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
    + else
    + mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK |
    + WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
    + er->config1 &= ~mask;
    + er->config1 |= (config & mask);
    + atomic_add(1 << (idx * 8), &er->ref);
    + ret = true;
    + }
    + raw_spin_unlock_irqrestore(&er->lock, flags);
    + return ret;
    +}
    +
    +static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx)
    +{
    + struct intel_uncore_extra_reg *er;
    +
    + if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
    + er = &box->shared_regs[idx];
    + atomic_dec(&er->ref);
    + return;
    + }
    +
    + idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
    + er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
    + atomic_sub(1 << (idx * 8), &er->ref);
    +}
    +
    +u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    + struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
    + int idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8);
    + u64 config = reg1->config;
    +
    + /* get the non-shared control bits and shift them */
    + idx = orig_idx - EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
    + if (uncore_nhmex)
    + config &= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
    + else
    + config &= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
    + if (new_idx > orig_idx) {
    + idx = new_idx - orig_idx;
    + config <<= 3 * idx;
    + } else {
    + idx = orig_idx - new_idx;
    + config >>= 3 * idx;
    + }
    + /* add the shared control bits back */
    + if (uncore_nhmex)
    + config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
    + else
    + config |= WSMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
    + if (modify) {
    + /* adjust the main event selector */
    + if (new_idx > orig_idx)
    + hwc->config += idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
    + else
    + hwc->config -= idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
    + reg1->config = config;
    + reg1->idx = ~0xff | new_idx;
    + }
    + return config;
    +}
    +
    +static struct event_constraint *
    +nhmex_mbox_get_constraint(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
    + struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
    + int i, idx[2], alloc = 0;
    + u64 config1 = reg1->config;
    +
    + idx[0] = __BITS_VALUE(reg1->idx, 0, 8);
    + idx[1] = __BITS_VALUE(reg1->idx, 1, 8);
    +again:
    + for (i = 0; i < 2; i++) {
    + if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
    + idx[i] = 0xff;
    +
    + if (idx[i] == 0xff)
    + continue;
    +
    + if (!nhmex_mbox_get_shared_reg(box, idx[i],
    + __BITS_VALUE(config1, i, 32)))
    + goto fail;
    + alloc |= (0x1 << i);
    + }
    +
    + /* for the match/mask registers */
    + if (reg2->idx != EXTRA_REG_NONE &&
    + (uncore_box_is_fake(box) || !reg2->alloc) &&
    + !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config))
    + goto fail;
    +
    + /*
    + * If it's a fake box -- as per validate_{group,event}() we
    + * shouldn't touch event state and we can avoid doing so
    + * since both will only call get_event_constraints() once
    + * on each event, this avoids the need for reg->alloc.
    + */
    + if (!uncore_box_is_fake(box)) {
    + if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8))
    + nhmex_mbox_alter_er(event, idx[0], true);
    + reg1->alloc |= alloc;
    + if (reg2->idx != EXTRA_REG_NONE)
    + reg2->alloc = 1;
    + }
    + return NULL;
    +fail:
    + if (idx[0] != 0xff && !(alloc & 0x1) &&
    + idx[0] >= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
    + /*
    + * events 0xd ~ 0x10 are functional identical, but are
    + * controlled by different fields in the ZDP_CTL_FVC
    + * register. If we failed to take one field, try the
    + * rest 3 choices.
    + */
    + BUG_ON(__BITS_VALUE(reg1->idx, 1, 8) != 0xff);
    + idx[0] -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
    + idx[0] = (idx[0] + 1) % 4;
    + idx[0] += EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
    + if (idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) {
    + config1 = nhmex_mbox_alter_er(event, idx[0], false);
    + goto again;
    + }
    + }
    +
    + if (alloc & 0x1)
    + nhmex_mbox_put_shared_reg(box, idx[0]);
    + if (alloc & 0x2)
    + nhmex_mbox_put_shared_reg(box, idx[1]);
    + return &constraint_empty;
    +}
    +
    +static void nhmex_mbox_put_constraint(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
    + struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
    +
    + if (uncore_box_is_fake(box))
    + return;
    +
    + if (reg1->alloc & 0x1)
    + nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8));
    + if (reg1->alloc & 0x2)
    + nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8));
    + reg1->alloc = 0;
    +
    + if (reg2->alloc) {
    + nhmex_mbox_put_shared_reg(box, reg2->idx);
    + reg2->alloc = 0;
    + }
    +}
    +
    +static int nhmex_mbox_extra_reg_idx(struct extra_reg *er)
    +{
    +
    + if (er->idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
    + return er->idx;
    + return er->idx + (er->event >> NHMEX_M_PMON_CTL_INC_SEL_SHIFT) - 0xd;
    +}
    +
    +static int nhmex_mbox_hw_config(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct intel_uncore_type *type = box->pmu->type;
    + struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
    + struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
    + struct extra_reg *er;
    + unsigned msr;
    + int reg_idx = 0;
    + /*
    + * The mbox events may require 2 extra MSRs at the most. But only
    + * the lower 32 bits in these MSRs are significant, so we can use
    + * config1 to pass two MSRs' config.
    + */
    + for (er = nhmex_uncore_mbox_extra_regs; er->msr; er++) {
    + if (er->event != (event->hw.config & er->config_mask))
    + continue;
    + if (event->attr.config1 & ~er->valid_mask)
    + return -EINVAL;
    +
    + msr = er->msr + type->msr_offset * box->pmu->pmu_idx;
    + if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff))
    + return -EINVAL;
    +
    + /* always use the 32~63 bits to pass the PLD config */
    + if (er->idx == EXTRA_REG_NHMEX_M_PLD)
    + reg_idx = 1;
    + else if (WARN_ON_ONCE(reg_idx > 0))
    + return -EINVAL;
    +
    + reg1->idx &= ~(0xff << (reg_idx * 8));
    + reg1->reg &= ~(0xffff << (reg_idx * 16));
    + reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8);
    + reg1->reg |= msr << (reg_idx * 16);
    + reg1->config = event->attr.config1;
    + reg_idx++;
    + }
    + /*
    + * The mbox only provides ability to perform address matching
    + * for the PLD events.
    + */
    + if (reg_idx == 2) {
    + reg2->idx = EXTRA_REG_NHMEX_M_FILTER;
    + if (event->attr.config2 & NHMEX_M_PMON_MM_CFG_EN)
    + reg2->config = event->attr.config2;
    + else
    + reg2->config = ~0ULL;
    + if (box->pmu->pmu_idx == 0)
    + reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG;
    + else
    + reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG;
    + }
    + return 0;
    +}
    +
    +static u64 nhmex_mbox_shared_reg_config(struct intel_uncore_box *box, int idx)
    +{
    + struct intel_uncore_extra_reg *er;
    + unsigned long flags;
    + u64 config;
    +
    + if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
    + return box->shared_regs[idx].config1;
    +
    + er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
    + raw_spin_lock_irqsave(&er->lock, flags);
    + config = er->config1;
    + raw_spin_unlock_irqrestore(&er->lock, flags);
    + return config;
    +}
    +
    +static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    + struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
    + struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
    + int idx;
    +
    + idx = __BITS_VALUE(reg1->idx, 0, 8);
    + if (idx != 0xff)
    + wrmsrl(__BITS_VALUE(reg1->reg, 0, 16),
    + nhmex_mbox_shared_reg_config(box, idx));
    + idx = __BITS_VALUE(reg1->idx, 1, 8);
    + if (idx != 0xff)
    + wrmsrl(__BITS_VALUE(reg1->reg, 1, 16),
    + nhmex_mbox_shared_reg_config(box, idx));
    +
    + if (reg2->idx != EXTRA_REG_NONE) {
    + wrmsrl(reg2->reg, 0);
    + if (reg2->config != ~0ULL) {
    + wrmsrl(reg2->reg + 1,
    + reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK);
    + wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK &
    + (reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT));
    + wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN);
    + }
    + }
    +
    + wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
    +}
    +
    +DEFINE_UNCORE_FORMAT_ATTR(count_mode, count_mode, "config:2-3");
    +DEFINE_UNCORE_FORMAT_ATTR(storage_mode, storage_mode, "config:4-5");
    +DEFINE_UNCORE_FORMAT_ATTR(wrap_mode, wrap_mode, "config:6");
    +DEFINE_UNCORE_FORMAT_ATTR(flag_mode, flag_mode, "config:7");
    +DEFINE_UNCORE_FORMAT_ATTR(inc_sel, inc_sel, "config:9-13");
    +DEFINE_UNCORE_FORMAT_ATTR(set_flag_sel, set_flag_sel, "config:19-21");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_cfg_en, filter_cfg_en, "config2:63");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_match, filter_match, "config2:0-33");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_mask, filter_mask, "config2:34-61");
    +DEFINE_UNCORE_FORMAT_ATTR(dsp, dsp, "config1:0-31");
    +DEFINE_UNCORE_FORMAT_ATTR(thr, thr, "config1:0-31");
    +DEFINE_UNCORE_FORMAT_ATTR(fvc, fvc, "config1:0-31");
    +DEFINE_UNCORE_FORMAT_ATTR(pgt, pgt, "config1:0-31");
    +DEFINE_UNCORE_FORMAT_ATTR(map, map, "config1:0-31");
    +DEFINE_UNCORE_FORMAT_ATTR(iss, iss, "config1:0-31");
    +DEFINE_UNCORE_FORMAT_ATTR(pld, pld, "config1:32-63");
    +
    +static struct attribute *nhmex_uncore_mbox_formats_attr[] = {
    + &format_attr_count_mode.attr,
    + &format_attr_storage_mode.attr,
    + &format_attr_wrap_mode.attr,
    + &format_attr_flag_mode.attr,
    + &format_attr_inc_sel.attr,
    + &format_attr_set_flag_sel.attr,
    + &format_attr_filter_cfg_en.attr,
    + &format_attr_filter_match.attr,
    + &format_attr_filter_mask.attr,
    + &format_attr_dsp.attr,
    + &format_attr_thr.attr,
    + &format_attr_fvc.attr,
    + &format_attr_pgt.attr,
    + &format_attr_map.attr,
    + &format_attr_iss.attr,
    + &format_attr_pld.attr,
    + NULL,
    +};
    +
    +static struct attribute_group nhmex_uncore_mbox_format_group = {
    + .name = "format",
    + .attrs = nhmex_uncore_mbox_formats_attr,
    +};
    +
    +static struct uncore_event_desc nhmex_uncore_mbox_events[] = {
    + INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x2800"),
    + INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x2820"),
    + { /* end: all zeroes */ },
    +};
    +
    +static struct uncore_event_desc wsmex_uncore_mbox_events[] = {
    + INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x5000"),
    + INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x5040"),
    + { /* end: all zeroes */ },
    +};
    +
    +static struct intel_uncore_ops nhmex_uncore_mbox_ops = {
    + NHMEX_UNCORE_OPS_COMMON_INIT(),
    + .enable_event = nhmex_mbox_msr_enable_event,
    + .hw_config = nhmex_mbox_hw_config,
    + .get_constraint = nhmex_mbox_get_constraint,
    + .put_constraint = nhmex_mbox_put_constraint,
    +};
    +
    +static struct intel_uncore_type nhmex_uncore_mbox = {
    + .name = "mbox",
    + .num_counters = 6,
    + .num_boxes = 2,
    + .perf_ctr_bits = 48,
    + .event_ctl = NHMEX_M0_MSR_PMU_CTL0,
    + .perf_ctr = NHMEX_M0_MSR_PMU_CNT0,
    + .event_mask = NHMEX_M_PMON_RAW_EVENT_MASK,
    + .box_ctl = NHMEX_M0_MSR_GLOBAL_CTL,
    + .msr_offset = NHMEX_M_MSR_OFFSET,
    + .pair_ctr_ctl = 1,
    + .num_shared_regs = 8,
    + .event_descs = wsmex_uncore_mbox_events,
    + .ops = &nhmex_uncore_mbox_ops,
    + .format_group = &nhmex_uncore_mbox_format_group,
    +};
    +
    +void nhmex_rbox_alter_er(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    + struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
    + int port;
    +
    + /* adjust the main event selector and extra register index */
    + if (reg1->idx % 2) {
    + reg1->idx--;
    + hwc->config -= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
    + } else {
    + reg1->idx++;
    + hwc->config += 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
    + }
    +
    + /* adjust extra register config */
    + port = reg1->idx / 6 + box->pmu->pmu_idx * 4;
    + switch (reg1->idx % 6) {
    + case 2:
    + /* shift the 8~15 bits to the 0~7 bits */
    + reg1->config >>= 8;
    + break;
    + case 3:
    + /* shift the 0~7 bits to the 8~15 bits */
    + reg1->config <<= 8;
    + break;
    + };
    +}
    +
    +/*
    + * Each rbox has 4 event set which monitor PQI port 0~3 or 4~7.
    + * An event set consists of 6 events, the 3rd and 4th events in
    + * an event set use the same extra register. So an event set uses
    + * 5 extra registers.
    + */
    +static struct event_constraint *
    +nhmex_rbox_get_constraint(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    + struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
    + struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
    + struct intel_uncore_extra_reg *er;
    + unsigned long flags;
    + int idx, er_idx;
    + u64 config1;
    + bool ok = false;
    +
    + if (!uncore_box_is_fake(box) && reg1->alloc)
    + return NULL;
    +
    + idx = reg1->idx % 6;
    + config1 = reg1->config;
    +again:
    + er_idx = idx;
    + /* the 3rd and 4th events use the same extra register */
    + if (er_idx > 2)
    + er_idx--;
    + er_idx += (reg1->idx / 6) * 5;
    +
    + er = &box->shared_regs[er_idx];
    + raw_spin_lock_irqsave(&er->lock, flags);
    + if (idx < 2) {
    + if (!atomic_read(&er->ref) || er->config1 == reg1->config) {
    + atomic_inc(&er->ref);
    + er->config1 = reg1->config;
    + ok = true;
    + }
    + } else if (idx == 2 || idx == 3) {
    + /*
    + * these two events use different fields in a extra register,
    + * the 0~7 bits and the 8~15 bits respectively.
    + */
    + u64 mask = 0xff << ((idx - 2) * 8);
    + if (!__BITS_VALUE(atomic_read(&er->ref), idx - 2, 8) ||
    + !((er->config1 ^ config1) & mask)) {
    + atomic_add(1 << ((idx - 2) * 8), &er->ref);
    + er->config1 &= ~mask;
    + er->config1 |= config1 & mask;
    + ok = true;
    + }
    + } else {
    + if (!atomic_read(&er->ref) ||
    + (er->config == (hwc->config >> 32) &&
    + er->config1 == reg1->config &&
    + er->config2 == reg2->config)) {
    + atomic_inc(&er->ref);
    + er->config = (hwc->config >> 32);
    + er->config1 = reg1->config;
    + er->config2 = reg2->config;
    + ok = true;
    + }
    + }
    + raw_spin_unlock_irqrestore(&er->lock, flags);
    +
    + if (!ok) {
    + /*
    + * The Rbox events are always in pairs. The paired
    + * events are functional identical, but use different
    + * extra registers. If we failed to take an extra
    + * register, try the alternative.
    + */
    + if (idx % 2)
    + idx--;
    + else
    + idx++;
    + if (idx != reg1->idx % 6) {
    + if (idx == 2)
    + config1 >>= 8;
    + else if (idx == 3)
    + config1 <<= 8;
    + goto again;
    + }
    + } else {
    + if (!uncore_box_is_fake(box)) {
    + if (idx != reg1->idx % 6)
    + nhmex_rbox_alter_er(box, event);
    + reg1->alloc = 1;
    + }
    + return NULL;
    + }
    + return &constraint_empty;
    +}
    +
    +static void nhmex_rbox_put_constraint(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct intel_uncore_extra_reg *er;
    + struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
    + int idx, er_idx;
    +
    + if (uncore_box_is_fake(box) || !reg1->alloc)
    + return;
    +
    + idx = reg1->idx % 6;
    + er_idx = idx;
    + if (er_idx > 2)
    + er_idx--;
    + er_idx += (reg1->idx / 6) * 5;
    +
    + er = &box->shared_regs[er_idx];
    + if (idx == 2 || idx == 3)
    + atomic_sub(1 << ((idx - 2) * 8), &er->ref);
    + else
    + atomic_dec(&er->ref);
    +
    + reg1->alloc = 0;
    +}
    +
    +static int nhmex_rbox_hw_config(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    + struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
    + struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
    + int idx;
    +
    + idx = (event->hw.config & NHMEX_R_PMON_CTL_EV_SEL_MASK) >>
    + NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
    + if (idx >= 0x18)
    + return -EINVAL;
    +
    + switch (idx % 6) {
    + case 4:
    + case 5:
    + hwc->config |= event->attr.config & (~0ULL << 32);
    + reg2->config = event->attr.config2;
    + break;
    + };
    +
    + reg1->config = event->attr.config1;
    + reg1->idx = idx;
    + return 0;
    +}
    +
    +static u64 nhmex_rbox_shared_reg_config(struct intel_uncore_box *box, int idx)
    +{
    + struct intel_uncore_extra_reg *er;
    + unsigned long flags;
    + u64 config;
    +
    + er = &box->shared_regs[idx];
    + raw_spin_lock_irqsave(&er->lock, flags);
    + config = er->config1;
    + raw_spin_unlock_irqrestore(&er->lock, flags);
    + return config;
    +}
    +
    +static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box,
    + struct perf_event *event)
    +{
    + struct hw_perf_event *hwc = &event->hw;
    + struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
    + struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
    + int idx, port;
    +
    + idx = reg1->idx;
    + port = idx / 6 + box->pmu->pmu_idx * 4;
    +
    + switch (idx % 6) {
    + case 0:
    + wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config);
    + break;
    + case 1:
    + wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config);
    + break;
    + case 2:
    + case 3:
    + wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port),
    + nhmex_rbox_shared_reg_config(box, 2 + (idx / 6) * 5));
    + break;
    + case 4:
    + wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port),
    + hwc->config >> 32);
    + wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config);
    + wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config);
    + break;
    + case 5:
    + wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port),
    + hwc->config >> 32);
    + wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);
    + wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);
    + break;
    + };
    +
    + wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
    + (hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));
    +}
    +
    +DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg, xbr_mm_cfg, "config:32-63");
    +DEFINE_UNCORE_FORMAT_ATTR(xbr_match, xbr_match, "config1:0-63");
    +DEFINE_UNCORE_FORMAT_ATTR(xbr_mask, xbr_mask, "config2:0-63");
    +DEFINE_UNCORE_FORMAT_ATTR(qlx_cfg, qlx_cfg, "config1:0-15");
    +DEFINE_UNCORE_FORMAT_ATTR(iperf_cfg, iperf_cfg, "config1:0-31");
    +
    +static struct attribute *nhmex_uncore_rbox_formats_attr[] = {
    + &format_attr_event5.attr,
    + &format_attr_xbr_mm_cfg.attr,
    + &format_attr_xbr_match.attr,
    + &format_attr_xbr_mask.attr,
    + &format_attr_qlx_cfg.attr,
    + &format_attr_iperf_cfg.attr,
    + NULL,
    +};
    +
    +static struct attribute_group nhmex_uncore_rbox_format_group = {
    + .name = "format",
    + .attrs = nhmex_uncore_rbox_formats_attr,
    +};
    +
    +static struct uncore_event_desc nhmex_uncore_rbox_events[] = {
    + INTEL_UNCORE_EVENT_DESC(qpi_0_2_flit_send,
    + "event=0x0,iperf_cfg=0x80000000"),
    + INTEL_UNCORE_EVENT_DESC(qpi_1_3_filt_send,
    + "event=0x6,iperf_cfg=0x80000000"),
    + INTEL_UNCORE_EVENT_DESC(qpi_0_2_idle_filt,
    + "event=0x0,iperf_cfg=0x40000000"),
    + INTEL_UNCORE_EVENT_DESC(qpi_1_3_idle_filt,
    + "event=0x6,iperf_cfg=0x40000000"),
    + INTEL_UNCORE_EVENT_DESC(qpi_0_2_date_response,
    + "event=0x0,iperf_cfg=0xc4"),
    + INTEL_UNCORE_EVENT_DESC(qpi_1_3_date_response,
    + "event=0x6,iperf_cfg=0xc4"),
    + { /* end: all zeroes */ },
    +};
    +
    +static struct intel_uncore_ops nhmex_uncore_rbox_ops = {
    + NHMEX_UNCORE_OPS_COMMON_INIT(),
    + .enable_event = nhmex_rbox_msr_enable_event,
    + .hw_config = nhmex_rbox_hw_config,
    + .get_constraint = nhmex_rbox_get_constraint,
    + .put_constraint = nhmex_rbox_put_constraint,
    +};
    +
    +static struct intel_uncore_type nhmex_uncore_rbox = {
    + .name = "rbox",
    + .num_counters = 8,
    + .num_boxes = 2,
    + .perf_ctr_bits = 48,
    + .event_ctl = NHMEX_R_MSR_PMON_CTL0,
    + .perf_ctr = NHMEX_R_MSR_PMON_CNT0,
    + .event_mask = NHMEX_R_PMON_RAW_EVENT_MASK,
    + .box_ctl = NHMEX_R_MSR_GLOBAL_CTL,
    + .msr_offset = NHMEX_R_MSR_OFFSET,
    + .pair_ctr_ctl = 1,
    + .num_shared_regs = 20,
    + .event_descs = nhmex_uncore_rbox_events,
    + .ops = &nhmex_uncore_rbox_ops,
    + .format_group = &nhmex_uncore_rbox_format_group
    +};
    +
    +static struct intel_uncore_type *nhmex_msr_uncores[] = {
    + &nhmex_uncore_ubox,
    + &nhmex_uncore_cbox,
    + &nhmex_uncore_bbox,
    + &nhmex_uncore_sbox,
    + &nhmex_uncore_mbox,
    + &nhmex_uncore_rbox,
    + &nhmex_uncore_wbox,
    + NULL,
    +};
    +/* end of Nehalem-EX/Westmere-EX uncore support */

    /* Sandy Bridge-EP uncore support */
    static struct intel_uncore_type snbep_uncore_cbox;
    @@ -150,16 +1266,6 @@ static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
    wrmsrl(hwc->config_base, hwc->config);
    }

    -static u64 snbep_uncore_msr_read_counter(struct intel_uncore_box *box,
    - struct perf_event *event)
    -{
    - struct hw_perf_event *hwc = &event->hw;
    - u64 count;
    -
    - rdmsrl(hwc->event_base, count);
    - return count;
    -}
    -
    static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
    {
    unsigned msr = uncore_msr_box_ctl(box);
    @@ -167,49 +1273,6 @@ static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
    wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
    }

    -static struct event_constraint *
    -snbep_uncore_get_constraint(struct intel_uncore_box *box,
    - struct perf_event *event)
    -{
    - struct intel_uncore_extra_reg *er;
    - struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
    - unsigned long flags;
    - bool ok = false;
    -
    - if (reg1->idx == EXTRA_REG_NONE || (box->phys_id >= 0 && reg1->alloc))
    - return NULL;
    -
    - er = &box->shared_regs[reg1->idx];
    - raw_spin_lock_irqsave(&er->lock, flags);
    - if (!atomic_read(&er->ref) || er->config1 == reg1->config) {
    - atomic_inc(&er->ref);
    - er->config1 = reg1->config;
    - ok = true;
    - }
    - raw_spin_unlock_irqrestore(&er->lock, flags);
    -
    - if (ok) {
    - if (box->phys_id >= 0)
    - reg1->alloc = 1;
    - return NULL;
    - }
    - return &constraint_empty;
    -}
    -
    -static void snbep_uncore_put_constraint(struct intel_uncore_box *box,
    - struct perf_event *event)
    -{
    - struct intel_uncore_extra_reg *er;
    - struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
    -
    - if (box->phys_id < 0 || !reg1->alloc)
    - return;
    -
    - er = &box->shared_regs[reg1->idx];
    - atomic_dec(&er->ref);
    - reg1->alloc = 0;
    -}
    -
    static int snbep_uncore_hw_config(struct intel_uncore_box *box,
    struct perf_event *event)
    {
    @@ -232,6 +1295,18 @@ static int snbep_uncore_hw_config(struct intel_uncore_box *box,
    return 0;
    }

    +DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
    +DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
    +DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_brand0, filter_brand0, "config1:0-7");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_brand1, filter_brand1, "config1:8-15");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_brand2, filter_brand2, "config1:16-23");
    +DEFINE_UNCORE_FORMAT_ATTR(filter_brand3, filter_brand3, "config1:24-31");
    +
    static struct attribute *snbep_uncore_formats_attr[] = {
    &format_attr_event.attr,
    &format_attr_umask.attr,
    @@ -320,9 +1395,9 @@ static struct intel_uncore_ops snbep_uncore_msr_ops = {
    .enable_box = snbep_uncore_msr_enable_box,
    .disable_event = snbep_uncore_msr_disable_event,
    .enable_event = snbep_uncore_msr_enable_event,
    - .read_counter = snbep_uncore_msr_read_counter,
    - .get_constraint = snbep_uncore_get_constraint,
    - .put_constraint = snbep_uncore_put_constraint,
    + .read_counter = uncore_msr_read_counter,
    + .get_constraint = uncore_get_constraint,
    + .put_constraint = uncore_put_constraint,
    .hw_config = snbep_uncore_hw_config,
    };

    @@ -603,7 +1678,6 @@ static void snbep_pci2phy_map_init(void)
    }
    /* end of Sandy Bridge-EP uncore support */

    -
    /* Sandy Bridge uncore support */
    static void snb_uncore_msr_enable_event(struct intel_uncore_box *box,
    struct perf_event *event)
    @@ -622,14 +1696,6 @@ static void snb_uncore_msr_disable_event(struct intel_uncore_box *box,
    wrmsrl(event->hw.config_base, 0);
    }

    -static u64 snb_uncore_msr_read_counter(struct intel_uncore_box *box,
    - struct perf_event *event)
    -{
    - u64 count;
    - rdmsrl(event->hw.event_base, count);
    - return count;
    -}
    -
    static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
    {
    if (box->pmu->pmu_idx == 0) {
    @@ -656,7 +1722,7 @@ static struct intel_uncore_ops snb_uncore_msr_ops = {
    .init_box = snb_uncore_msr_init_box,
    .disable_event = snb_uncore_msr_disable_event,
    .enable_event = snb_uncore_msr_enable_event,
    - .read_counter = snb_uncore_msr_read_counter,
    + .read_counter = uncore_msr_read_counter,
    };

    static struct event_constraint snb_uncore_cbox_constraints[] = {
    @@ -744,7 +1810,7 @@ static struct intel_uncore_ops nhm_uncore_msr_ops = {
    .enable_box = nhm_uncore_msr_enable_box,
    .disable_event = snb_uncore_msr_disable_event,
    .enable_event = nhm_uncore_msr_enable_event,
    - .read_counter = snb_uncore_msr_read_counter,
    + .read_counter = uncore_msr_read_counter,
    };

    static struct intel_uncore_type nhm_uncore = {
    @@ -1256,6 +2322,7 @@ int uncore_pmu_event_init(struct perf_event *event)
    event->hw.idx = -1;
    event->hw.last_tag = ~0ULL;
    event->hw.extra_reg.idx = EXTRA_REG_NONE;
    + event->hw.branch_reg.idx = EXTRA_REG_NONE;

    if (event->attr.config == UNCORE_FIXED_EVENT) {
    /* no fixed counter */
    @@ -1752,9 +2819,9 @@ static int __init uncore_cpu_init(void)
    max_cores = boot_cpu_data.x86_max_cores;
    switch (boot_cpu_data.x86_model) {
    case 26: /* Nehalem */
    - case 30:
    + case 30: /* Nehalem-EP */
    case 37: /* Westmere */
    - case 44:
    + case 44: /* Westmere-EP */
    msr_uncores = nhm_msr_uncores;
    break;
    case 42: /* Sandy Bridge */
    @@ -1767,6 +2834,14 @@ static int __init uncore_cpu_init(void)
    snbep_uncore_cbox.num_boxes = max_cores;
    msr_uncores = snbep_msr_uncores;
    break;
    + case 46: /* Nehalem-EX */
    + uncore_nhmex = true;
    + nhmex_uncore_mbox.event_descs = nhmex_uncore_mbox_events;
    + case 47: /* Westmere-EX aka. Xeon E7 */
    + if (nhmex_uncore_cbox.num_boxes > max_cores)
    + nhmex_uncore_cbox.num_boxes = max_cores;
    + msr_uncores = nhmex_msr_uncores;
    + break;
    default:
    return 0;
    }
    diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
    index b13e9ea..8f18131 100644
    --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
    +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
    @@ -5,8 +5,6 @@
    #include "perf_event.h"

    #define UNCORE_PMU_NAME_LEN 32
    -#define UNCORE_BOX_HASH_SIZE 8
    -
    #define UNCORE_PMU_HRTIMER_INTERVAL (60 * NSEC_PER_SEC)

    #define UNCORE_FIXED_EVENT 0xff
    @@ -158,6 +156,188 @@
    #define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
    #define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd

    +/* NHM-EX event control */
    +#define NHMEX_PMON_CTL_EV_SEL_MASK 0x000000ff
    +#define NHMEX_PMON_CTL_UMASK_MASK 0x0000ff00
    +#define NHMEX_PMON_CTL_EN_BIT0 (1 << 0)
    +#define NHMEX_PMON_CTL_EDGE_DET (1 << 18)
    +#define NHMEX_PMON_CTL_PMI_EN (1 << 20)
    +#define NHMEX_PMON_CTL_EN_BIT22 (1 << 22)
    +#define NHMEX_PMON_CTL_INVERT (1 << 23)
    +#define NHMEX_PMON_CTL_TRESH_MASK 0xff000000
    +#define NHMEX_PMON_RAW_EVENT_MASK (NHMEX_PMON_CTL_EV_SEL_MASK | \
    + NHMEX_PMON_CTL_UMASK_MASK | \
    + NHMEX_PMON_CTL_EDGE_DET | \
    + NHMEX_PMON_CTL_INVERT | \
    + NHMEX_PMON_CTL_TRESH_MASK)
    +
    +/* NHM-EX Ubox */
    +#define NHMEX_U_MSR_PMON_GLOBAL_CTL 0xc00
    +#define NHMEX_U_MSR_PMON_CTR 0xc11
    +#define NHMEX_U_MSR_PMON_EV_SEL 0xc10
    +
    +#define NHMEX_U_PMON_GLOBAL_EN (1 << 0)
    +#define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL 0x0000001e
    +#define NHMEX_U_PMON_GLOBAL_EN_ALL (1 << 28)
    +#define NHMEX_U_PMON_GLOBAL_RST_ALL (1 << 29)
    +#define NHMEX_U_PMON_GLOBAL_FRZ_ALL (1 << 31)
    +
    +#define NHMEX_U_PMON_RAW_EVENT_MASK \
    + (NHMEX_PMON_CTL_EV_SEL_MASK | \
    + NHMEX_PMON_CTL_EDGE_DET)
    +
    +/* NHM-EX Cbox */
    +#define NHMEX_C0_MSR_PMON_GLOBAL_CTL 0xd00
    +#define NHMEX_C0_MSR_PMON_CTR0 0xd11
    +#define NHMEX_C0_MSR_PMON_EV_SEL0 0xd10
    +#define NHMEX_C_MSR_OFFSET 0x20
    +
    +/* NHM-EX Bbox */
    +#define NHMEX_B0_MSR_PMON_GLOBAL_CTL 0xc20
    +#define NHMEX_B0_MSR_PMON_CTR0 0xc31
    +#define NHMEX_B0_MSR_PMON_CTL0 0xc30
    +#define NHMEX_B_MSR_OFFSET 0x40
    +#define NHMEX_B0_MSR_MATCH 0xe45
    +#define NHMEX_B0_MSR_MASK 0xe46
    +#define NHMEX_B1_MSR_MATCH 0xe4d
    +#define NHMEX_B1_MSR_MASK 0xe4e
    +
    +#define NHMEX_B_PMON_CTL_EN (1 << 0)
    +#define NHMEX_B_PMON_CTL_EV_SEL_SHIFT 1
    +#define NHMEX_B_PMON_CTL_EV_SEL_MASK \
    + (0x1f << NHMEX_B_PMON_CTL_EV_SEL_SHIFT)
    +#define NHMEX_B_PMON_CTR_SHIFT 6
    +#define NHMEX_B_PMON_CTR_MASK \
    + (0x3 << NHMEX_B_PMON_CTR_SHIFT)
    +#define NHMEX_B_PMON_RAW_EVENT_MASK \
    + (NHMEX_B_PMON_CTL_EV_SEL_MASK | \
    + NHMEX_B_PMON_CTR_MASK)
    +
    +/* NHM-EX Sbox */
    +#define NHMEX_S0_MSR_PMON_GLOBAL_CTL 0xc40
    +#define NHMEX_S0_MSR_PMON_CTR0 0xc51
    +#define NHMEX_S0_MSR_PMON_CTL0 0xc50
    +#define NHMEX_S_MSR_OFFSET 0x80
    +#define NHMEX_S0_MSR_MM_CFG 0xe48
    +#define NHMEX_S0_MSR_MATCH 0xe49
    +#define NHMEX_S0_MSR_MASK 0xe4a
    +#define NHMEX_S1_MSR_MM_CFG 0xe58
    +#define NHMEX_S1_MSR_MATCH 0xe59
    +#define NHMEX_S1_MSR_MASK 0xe5a
    +
    +#define NHMEX_S_PMON_MM_CFG_EN (0x1ULL << 63)
    +#define NHMEX_S_EVENT_TO_R_PROG_EV 0
    +
    +/* NHM-EX Mbox */
    +#define NHMEX_M0_MSR_GLOBAL_CTL 0xca0
    +#define NHMEX_M0_MSR_PMU_DSP 0xca5
    +#define NHMEX_M0_MSR_PMU_ISS 0xca6
    +#define NHMEX_M0_MSR_PMU_MAP 0xca7
    +#define NHMEX_M0_MSR_PMU_MSC_THR 0xca8
    +#define NHMEX_M0_MSR_PMU_PGT 0xca9
    +#define NHMEX_M0_MSR_PMU_PLD 0xcaa
    +#define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC 0xcab
    +#define NHMEX_M0_MSR_PMU_CTL0 0xcb0
    +#define NHMEX_M0_MSR_PMU_CNT0 0xcb1
    +#define NHMEX_M_MSR_OFFSET 0x40
    +#define NHMEX_M0_MSR_PMU_MM_CFG 0xe54
    +#define NHMEX_M1_MSR_PMU_MM_CFG 0xe5c
    +
    +#define NHMEX_M_PMON_MM_CFG_EN (1ULL << 63)
    +#define NHMEX_M_PMON_ADDR_MATCH_MASK 0x3ffffffffULL
    +#define NHMEX_M_PMON_ADDR_MASK_MASK 0x7ffffffULL
    +#define NHMEX_M_PMON_ADDR_MASK_SHIFT 34
    +
    +#define NHMEX_M_PMON_CTL_EN (1 << 0)
    +#define NHMEX_M_PMON_CTL_PMI_EN (1 << 1)
    +#define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT 2
    +#define NHMEX_M_PMON_CTL_COUNT_MODE_MASK \
    + (0x3 << NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT)
    +#define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT 4
    +#define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK \
    + (0x3 << NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT)
    +#define NHMEX_M_PMON_CTL_WRAP_MODE (1 << 6)
    +#define NHMEX_M_PMON_CTL_FLAG_MODE (1 << 7)
    +#define NHMEX_M_PMON_CTL_INC_SEL_SHIFT 9
    +#define NHMEX_M_PMON_CTL_INC_SEL_MASK \
    + (0x1f << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
    +#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT 19
    +#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK \
    + (0x7 << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT)
    +#define NHMEX_M_PMON_RAW_EVENT_MASK \
    + (NHMEX_M_PMON_CTL_COUNT_MODE_MASK | \
    + NHMEX_M_PMON_CTL_STORAGE_MODE_MASK | \
    + NHMEX_M_PMON_CTL_WRAP_MODE | \
    + NHMEX_M_PMON_CTL_FLAG_MODE | \
    + NHMEX_M_PMON_CTL_INC_SEL_MASK | \
    + NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)
    +
    +#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK (((1 << 11) - 1) | (1 << 23))
    +#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (11 + 3 * (n)))
    +
    +#define WSMEX_M_PMON_ZDP_CTL_FVC_MASK (((1 << 12) - 1) | (1 << 24))
    +#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (12 + 3 * (n)))
    +
    +/*
    + * use the 9~13 bits to select event If the 7th bit is not set,
    + * otherwise use the 19~21 bits to select event.
    + */
    +#define MBOX_INC_SEL(x) ((x) << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
    +#define MBOX_SET_FLAG_SEL(x) (((x) << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT) | \
    + NHMEX_M_PMON_CTL_FLAG_MODE)
    +#define MBOX_INC_SEL_MASK (NHMEX_M_PMON_CTL_INC_SEL_MASK | \
    + NHMEX_M_PMON_CTL_FLAG_MODE)
    +#define MBOX_SET_FLAG_SEL_MASK (NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK | \
    + NHMEX_M_PMON_CTL_FLAG_MODE)
    +#define MBOX_INC_SEL_EXTAR_REG(c, r) \
    + EVENT_EXTRA_REG(MBOX_INC_SEL(c), NHMEX_M0_MSR_PMU_##r, \
    + MBOX_INC_SEL_MASK, (u64)-1, NHMEX_M_##r)
    +#define MBOX_SET_FLAG_SEL_EXTRA_REG(c, r) \
    + EVENT_EXTRA_REG(MBOX_SET_FLAG_SEL(c), NHMEX_M0_MSR_PMU_##r, \
    + MBOX_SET_FLAG_SEL_MASK, \
    + (u64)-1, NHMEX_M_##r)
    +
    +/* NHM-EX Rbox */
    +#define NHMEX_R_MSR_GLOBAL_CTL 0xe00
    +#define NHMEX_R_MSR_PMON_CTL0 0xe10
    +#define NHMEX_R_MSR_PMON_CNT0 0xe11
    +#define NHMEX_R_MSR_OFFSET 0x20
    +
    +#define NHMEX_R_MSR_PORTN_QLX_CFG(n) \
    + ((n) < 4 ? (0xe0c + (n)) : (0xe2c + (n) - 4))
    +#define NHMEX_R_MSR_PORTN_IPERF_CFG0(n) (0xe04 + (n))
    +#define NHMEX_R_MSR_PORTN_IPERF_CFG1(n) (0xe24 + (n))
    +#define NHMEX_R_MSR_PORTN_XBR_OFFSET(n) \
    + (((n) < 4 ? 0 : 0x10) + (n) * 4)
    +#define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) \
    + (0xe60 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
    +#define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(n) \
    + (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 1)
    +#define NHMEX_R_MSR_PORTN_XBR_SET1_MASK(n) \
    + (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 2)
    +#define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) \
    + (0xe70 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
    +#define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(n) \
    + (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 1)
    +#define NHMEX_R_MSR_PORTN_XBR_SET2_MASK(n) \
    + (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 2)
    +
    +#define NHMEX_R_PMON_CTL_EN (1 << 0)
    +#define NHMEX_R_PMON_CTL_EV_SEL_SHIFT 1
    +#define NHMEX_R_PMON_CTL_EV_SEL_MASK \
    + (0x1f << NHMEX_R_PMON_CTL_EV_SEL_SHIFT)
    +#define NHMEX_R_PMON_CTL_PMI_EN (1 << 6)
    +#define NHMEX_R_PMON_RAW_EVENT_MASK NHMEX_R_PMON_CTL_EV_SEL_MASK
    +
    +/* NHM-EX Wbox */
    +#define NHMEX_W_MSR_GLOBAL_CTL 0xc80
    +#define NHMEX_W_MSR_PMON_CNT0 0xc90
    +#define NHMEX_W_MSR_PMON_EVT_SEL0 0xc91
    +#define NHMEX_W_MSR_PMON_FIXED_CTR 0x394
    +#define NHMEX_W_MSR_PMON_FIXED_CTL 0x395
    +
    +#define NHMEX_W_PMON_GLOBAL_FIXED_EN (1ULL << 31)
    +
    struct intel_uncore_ops;
    struct intel_uncore_pmu;
    struct intel_uncore_box;
    @@ -178,6 +358,8 @@ struct intel_uncore_type {
    unsigned msr_offset;
    unsigned num_shared_regs:8;
    unsigned single_fixed:1;
    + unsigned pair_ctr_ctl:1;
    + unsigned *msr_offsets;
    struct event_constraint unconstrainted;
    struct event_constraint *constraints;
    struct intel_uncore_pmu *pmus;
    @@ -213,7 +395,7 @@ struct intel_uncore_pmu {

    struct intel_uncore_extra_reg {
    raw_spinlock_t lock;
    - u64 config1;
    + u64 config, config1, config2;
    atomic_t ref;
    };

    @@ -295,43 +477,47 @@ unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
    return idx * 8 + box->pmu->type->perf_ctr;
    }

    -static inline
    -unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
    +static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
    +{
    + struct intel_uncore_pmu *pmu = box->pmu;
    + return pmu->type->msr_offsets ?
    + pmu->type->msr_offsets[pmu->pmu_idx] :
    + pmu->type->msr_offset * pmu->pmu_idx;
    +}
    +
    +static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
    {
    if (!box->pmu->type->box_ctl)
    return 0;
    - return box->pmu->type->box_ctl +
    - box->pmu->type->msr_offset * box->pmu->pmu_idx;
    + return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
    }

    -static inline
    -unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
    +static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
    {
    if (!box->pmu->type->fixed_ctl)
    return 0;
    - return box->pmu->type->fixed_ctl +
    - box->pmu->type->msr_offset * box->pmu->pmu_idx;
    + return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
    }

    -static inline
    -unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
    +static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
    {
    - return box->pmu->type->fixed_ctr +
    - box->pmu->type->msr_offset * box->pmu->pmu_idx;
    + return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
    }

    static inline
    unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
    {
    - return idx + box->pmu->type->event_ctl +
    - box->pmu->type->msr_offset * box->pmu->pmu_idx;
    + return box->pmu->type->event_ctl +
    + (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
    + uncore_msr_box_offset(box);
    }

    static inline
    unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
    {
    - return idx + box->pmu->type->perf_ctr +
    - box->pmu->type->msr_offset * box->pmu->pmu_idx;
    + return box->pmu->type->perf_ctr +
    + (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
    + uncore_msr_box_offset(box);
    }

    static inline
    @@ -422,3 +608,8 @@ static inline void uncore_box_init(struct intel_uncore_box *box)
    box->pmu->type->ops->init_box(box);
    }
    }
    +
    +static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
    +{
    + return (box->phys_id < 0);
    +}
    --
    1.7.10.4


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