Messages in this thread | | | Date | Wed, 6 Jun 2012 16:58:27 -0700 | From | Chris Wright <> | Subject | Re: [PATCH 2/2] iommu: dmar -- reserve mmio space used by IOMMU |
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* David Woodhouse (dwmw2@infradead.org) wrote: > On Mon, 2012-06-04 at 19:09 -0400, Don Dutile wrote: > > How does the kernel probe for chipsets, then registers with the chipsets > > to find the programmed IOMMU BAR values? > > -- I missed that class.... I only have Intel Virt Tech Directed I/O > > Architecture spec., and the beginning of IOMMU is based on DMAR tables... > > If you have more info/guidance, I'd appreciate it. > > Hm, I thought we'd already started doing some of that in order to > sanity-check the DMAR tables. The VTBAR registers are in PCI config > space. The quirk_ioat_snb_local_iommu() check is already looking at > them...
I always had the impression that things like VTBAR registers are entirely chipset specific (and may not be there for all chipsets). Would be great if that's incorrect. Any idea?
thanks, -chris
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