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    SubjectRe: git bisect and perf
    On Tue, 2012-06-05 at 11:12 -0600, David Ahern wrote:
    > On 6/5/12 10:05 AM, Peter Zijlstra wrote:
    > > On Tue, 2012-06-05 at 18:00 +0200, Peter Zijlstra wrote:
    > >> On Tue, 2012-06-05 at 09:29 -0600, David Ahern wrote:
    > >>> I am trying find out when (ie. which commit) the pebs feature
    > >>> actually
    > >>> started working on a westmere system
    > >>
    > >> What do you mean with working? The whole cycles:pp thing is magic and
    > >> unrelated to 'regular' PEBS stuff.
    > :p requires PEBS?

    On Intel it does.. On AMD you want IBS for that.

    Note that on Intel there's a difference between :p and :pp.

    From perf_event_attr:

    * precise_ip:
    * 0 - SAMPLE_IP can have arbitrary skid
    * 1 - SAMPLE_IP must have constant skid
    * 2 - SAMPLE_IP requested to have 0 skid
    * 3 - SAMPLE_IP must have 0 skid
    precise_ip : 2, /* skid constraint */

    So 0 being the default (no :p) we use the regular PMI and provide the IP
    from the spot that served the exception. This can be a few instructions
    _after_ the instruction that triggered the event overflow.

    1 (:p) means constant skid, for Intel this maps to regular PEBS and
    returns the IP as provided by the PEBS record. This is one instruction
    after the instruction that caused the event overflow (because the PEBS
    hardware assist triggers when we're executing the instruction that
    triggered it, it needs to have already fetched the instruction and
    incremented the IP etc..).

    2 (:pp) requests 0 skid, since PEBS provides IP + 1 instruction, we need
    to rewind the instruction stream. In order to do this we use the LBR in
    conjunction with a FREEZE_LBR_ON_PMI feature from DEBUG_CTL and limit
    the PEBS buffer to a single entry. So when we get the PEBS buffer full
    PMI, we read the LBR, find the start of the most recent basic block (to
    address of the last branch) and decode the instruction stream until we
    find the current IP. Then we know the IP that caused it is the previous
    one. Tada!

    We set the PERF_RECORD_MISC_EXACT_IP bit when the rewind worked and we
    can guarantee 0 skid (+- hardware bugs, of which there are a few).

    3 (:ppp) would require 0 skid, but since the unwind using LBR isn't a
    guaranteed thing we don't implement this for Intel (or anybody else for
    that matter afaik).

    Now not all events the Intel PMU can do are PEBS capable; in fact most
    aren't. So the whole cycles thing is about mapping the regular cycles
    event to something that is PEBS capable.

     \ /
      Last update: 2012-06-05 20:01    [W:0.032 / U:46.008 seconds]
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