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Subject[PATCH v9 0/9] x86 tlb optimisation and clean up
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Update to V9 version. This version is mainly for commit change.

1, It split the 6th patch into 6th and 7th for one patch to one issue.

2, update commit log for the 7th patch to include Yongjie's testing
results, I don't know why lkml can not show the e-mail, maybe some
words make it looks as spam?, Anyway I believe guys in to/cc list
have the data. So, attached the e-mail contents into log.

3, change commit log for 8th, 9th to include most clear explaination
and detailed testing result.


This patch set has clear performance gain, and clean up IDT table.

It is also quite safe after many review comments from Peter Anvin,
PeterZ, Nick Piggin, Steven Rostedt, Andi Kleen and Borislav etc.
And it runs well with my long time performance testing...

Anyone like to give the reason if it is not readly for upstream?

Best Regards!
Alex


[PATCH v9 1/9] x86/tlb_info: get last level TLB entry number of CPU
[PATCH v9 2/9] x86/flush_tlb: try flush_tlb_single one by one in
[PATCH v9 3/9] x86/tlb: fall back to flush all when meet a THP large
[PATCH v9 4/9] x86/tlb: add tlb_flushall_shift for specific CPU
[PATCH v9 5/9] x86/tlb: add tlb_flushall_shift knob into debugfs
[PATCH v9 6/9] mm/mmu_gather: enable tlb flush range in generic
[PATCH v9 7/9] x86/tlb: enable tlb flush range support for x86
[PATCH v9 8/9] x86/tlb: replace INVALIDATE_TLB_VECTOR by
[PATCH v9 9/9] x86/tlb: do flush_tlb_kernel_range by 'invlpg'


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