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    Subject[ 05/61] drm/radeon: add some additional 6xx/7xx/EG register init
    3.4-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Alex Deucher <alexander.deucher@amd.com>

    commit b866d1334ba2d544bc575d75357dea6bdcdc7f46 upstream.

    - SMX_SAR_CTL0 needs to be programmed correctly to prevent
    problems with memory exports in certain cases.
    - VC_ENHANCE needs to be initialized on 6xx/7xx.

    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Dave Airlie <airlied@redhat.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/gpu/drm/radeon/evergreen.c | 3 +++
    drivers/gpu/drm/radeon/evergreend.h | 1 +
    drivers/gpu/drm/radeon/r600.c | 1 +
    drivers/gpu/drm/radeon/r600d.h | 1 +
    drivers/gpu/drm/radeon/rv770.c | 5 ++++-
    drivers/gpu/drm/radeon/rv770d.h | 3 +++
    6 files changed, 13 insertions(+), 1 deletion(-)

    --- a/drivers/gpu/drm/radeon/evergreen.c
    +++ b/drivers/gpu/drm/radeon/evergreen.c
    @@ -2210,6 +2210,9 @@ static void evergreen_gpu_init(struct ra
    smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
    WREG32(SMX_DC_CTL0, smx_dc_ctl0);

    + if (rdev->family <= CHIP_SUMO2)
    + WREG32(SMX_SAR_CTL0, 0x00010000);
    +
    WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
    POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
    SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
    --- a/drivers/gpu/drm/radeon/evergreend.h
    +++ b/drivers/gpu/drm/radeon/evergreend.h
    @@ -273,6 +273,7 @@
    #define SCRATCH_UMSK 0x8540
    #define SCRATCH_ADDR 0x8544

    +#define SMX_SAR_CTL0 0xA008
    #define SMX_DC_CTL0 0xA020
    #define USE_HASH_FUNCTION (1 << 0)
    #define NUMBER_OF_SETS(x) ((x) << 1)
    --- a/drivers/gpu/drm/radeon/r600.c
    +++ b/drivers/gpu/drm/radeon/r600.c
    @@ -1906,6 +1906,7 @@ void r600_gpu_init(struct radeon_device
    WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
    NUM_CLIP_SEQ(3)));
    WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
    + WREG32(VC_ENHANCE, 0);
    }


    --- a/drivers/gpu/drm/radeon/r600d.h
    +++ b/drivers/gpu/drm/radeon/r600d.h
    @@ -483,6 +483,7 @@
    #define TC_L2_SIZE(x) ((x)<<5)
    #define L2_DISABLE_LATE_HIT (1<<9)

    +#define VC_ENHANCE 0x9714

    #define VGT_CACHE_INVALIDATION 0x88C4
    #define CACHE_INVALIDATION(x) ((x)<<0)
    --- a/drivers/gpu/drm/radeon/rv770.c
    +++ b/drivers/gpu/drm/radeon/rv770.c
    @@ -782,6 +782,9 @@ static void rv770_gpu_init(struct radeon
    ACK_FLUSH_CTL(3) |
    SYNC_FLUSH_CTL));

    + if (rdev->family != CHIP_RV770)
    + WREG32(SMX_SAR_CTL0, 0x00003f3f);
    +
    db_debug3 = RREG32(DB_DEBUG3);
    db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
    switch (rdev->family) {
    @@ -960,7 +963,7 @@ static void rv770_gpu_init(struct radeon

    WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
    NUM_CLIP_SEQ(3)));
    -
    + WREG32(VC_ENHANCE, 0);
    }

    void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
    --- a/drivers/gpu/drm/radeon/rv770d.h
    +++ b/drivers/gpu/drm/radeon/rv770d.h
    @@ -208,6 +208,7 @@
    #define SCRATCH_UMSK 0x8540
    #define SCRATCH_ADDR 0x8544

    +#define SMX_SAR_CTL0 0xA008
    #define SMX_DC_CTL0 0xA020
    #define USE_HASH_FUNCTION (1 << 0)
    #define CACHE_DEPTH(x) ((x) << 1)
    @@ -307,6 +308,8 @@
    #define TCP_CNTL 0x9610
    #define TCP_CHAN_STEER 0x9614

    +#define VC_ENHANCE 0x9714
    +
    #define VGT_CACHE_INVALIDATION 0x88C4
    #define CACHE_INVALIDATION(x) ((x)<<0)
    #define VC_ONLY 0



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