Messages in this thread | | | Date | Wed, 20 Jun 2012 14:29:41 +0200 | From | Robert Richter <> | Subject | Re: [PATCH 00/10] perf, x86: Add northbridge counter support for AMD family 15h |
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On 20.06.12 12:16:13, Peter Zijlstra wrote: > Sure it can be done, just not pretty. Combine that with all the other > special casing like patches 3 and 10 and one really starts to wonder if > its all worth it.
I actually started writing the code by implementing a different pmu. It turned out to be the wrong direction. The pmus would be almost identical, just some different config values and a bit nb related special code. But you can't really reuse the functions on a 2nd running pmu, there are hard wired functions in the x86 pmu code and x86_pmu ops do not fit for such a split. It would mean a complete rework of x86 perf code. Really, I tried that already. And all this effort just to implement nb counters? If someone is willing to help here this would be ok, but I guess I would have to do all this on my own. And to be fair, this effort was also not make for fixed counters, pebs, bts, etc. Maybe the uncore implementation is different here, but today is the first day the uncore patches are in tip.
I also do not see the advantage of a separate pmu. Just to have a different msr base to avoid the use of counter masks and some optimized pmu ops? Masks are wide spread used in the kernel and on x86 the bsf instruction takes not more than an increment. And switches in the code paths to special nb code are not more expensive than other switches for other special code.
-Robert
-- Advanced Micro Devices, Inc. Operating System Research Center
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