| | Date | Tue, 12 Jun 2012 10:14:16 +0200 | | Subject | Re: [PATCH] perf/x86: check ucode before disabling PEBS on SandyBridge | | From | Stephane Eranian <> |
| |
On Fri, Jun 8, 2012 at 4:25 PM, Peter Zijlstra <peterz@infradead.org> wrote: > > On Fri, 2012-06-08 at 16:07 +0200, Stephane Eranian wrote: > > > +static const u32 snb_ucode_rev = 0x28; > > > + > > > > That needs to be a per CPU model value. It > > is not the same for SNB vs. SNB-EP. On EP > > it may even depends on stepping. > > Yeah, you said, easiest is removing the const and putting some > assignments to the thing somewhere in our model switch. > > Do you know what values for what chip we should use? >
Ok, so to close on this, I tried the 6/6/2012 ucode update on a few SNB-EP systems.
I got two answers depending on the stepping: C1 (stepping 6) -> 0x618 C2 (stepping 7) -> 0x70c
So we need to check x86_mask for stepping and adjust the value of snb_ucode_rev accordingly for model 45.
|