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    SubjectRe: [PATCHv4 3/5] kvm: host side for eoi optimization
    On 05/16/2012 02:46 PM, Michael S. Tsirkin wrote:
    > Implementation of PV EOI using shared memory.
    > This reduces the number of exits an interrupt
    > causes as much as by half.
    >
    > The idea is simple: there's a bit, per APIC, in guest memory,
    > that tells the guest that it does not need EOI.
    > We set it before injecting an interrupt and clear
    > before injecting a nested one. Guest tests it using
    > a test and clear operation - this is necessary
    > so that host can detect interrupt nesting -
    > and if set, it can skip the EOI MSR.
    >
    > There's a new MSR to set the address of said register
    > in guest memory. Otherwise not much changed:
    > - Guest EOI is not required
    > - Register is tested & ISR is automatically cleared on exit
    >
    > For testing results see description of previous patch
    > 'kvm_para: guest side for eoi avoidance'.
    >
    >
    > + /*
    > + * It's legal for guest to ignore the PV EOI optimization
    > + * and signal EOI by APIC write. If this happens, clear
    > + * PV EOI on guest's behalf.
    > + */
    > + if (pv_eoi_enabled(apic->vcpu))
    > + pv_eoi_clr_pending(apic->vcpu);

    I'm a little worried about all the clr_pending() calls scattered
    around. What happens if we forget one? In particular, we might miss
    one on nested vmentry.

    A safer path is to always clear it, but to enable it again during
    reentry if all conditions are satisified. Might be a little slower though.

    --
    error compiling committee.c: too many arguments to function



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