Messages in this thread |  | | | Date | Mon, 9 Apr 2012 10:11:19 -0700 | | From | Jesse Barnes <> | | Subject | Re: i915_driver_irq_handler: irq 42: nobody cared |
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On Fri, 30 Mar 2012 11:45:43 +0100 Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Fri, 30 Mar 2012 11:59:28 +0200, Jiri Slaby <jslaby@suse.cz> wrote: > > I don't know what to dump more, because iir is obviously zero too. What > > other sources of interrupts are on the (G33) chip? > > IIR is the master interrupt, with chained secondary interrupt statuses. > If IIR is 0, the interrupt wasn't raised by the GPU.
I've actually seen cases where one of the PIPE*STAT regs is stuck, and even if IIR is 0 we still get interrupts... Jiri can you verify the PIPE*STAT regs have bits set, maybe one or more we don't check for?
-- Jesse Barnes, Intel Open Source Technology Center [unhandled content-type:application/pgp-signature] |  |