Messages in this thread | | | From | Chris Wilson <> | Subject | Re: [PATCH 14/14 v5] drm/i915/intel_i2c: remove POSTING_READ() from gmbus transfers | Date | Wed, 28 Mar 2012 15:30:13 +0100 |
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On Wed, 28 Mar 2012 21:21:42 +0800, Daniel Kurtz <djkurtz@chromium.org> wrote: > On Wed, Mar 28, 2012 at 9:05 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > We do need the write flush here (and set_data) as the next action is a > > udelay loop which is not per-se a mb. > > Now I am confused. I915_WRITE_NOTRACE() calls writel(), which has an > explicit mb(); Why do you need another mb?
Nominally writel isn't a memory barrier. I see that x86 does include mb in its writel define. However, if memory serves, that is only a write barrier to memory (equivalent of mfence), and not a PCI write flush/barrier for which we need to an explicit PCI read. -Chris
-- Chris Wilson, Intel Open Source Technology Centre
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