Messages in this thread | | | Date | Wed, 21 Mar 2012 18:49:19 +0100 | From | Wolfram Sang <> | Subject | Re: [PATCH] Support M95040 SPI EEPROM |
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On Wed, Mar 21, 2012 at 10:30:22AM -0700, Chris Wright wrote: > * Ivo Sieben (meltedpianoman@gmail.com) wrote: > > Updated the generic SPI EEPROM driver AT25 for support of address bit A8 > > in the instruction byte. Certain EEPROMS (like M95040 from ST) have a 512 > > Byte size but use only one address byte (A0 to A7) for addressing. For the > > extra address bit A8 bit 3 of the instruction byte is used. This instruction > > bit is threated as don't care for other AT25 like chips > > The AT25 datasheet lists that bit in READ and PROGRAM(write) as don't > care, and the MV950x0 datasheet says just what you've said above (BTW, > it's "treated" not "threated"). How confident are you that this logic > will not cause problems for existing non-MV95040 chips?
I was thinking the same. We should not make this behaviour default, but optional. My idea would be another flag, i.e. EE_INSTR_BIT3_IS_ADDR. I'd think the code could then also easily be written in a way, that it gives 17 and 25 bit addresses for free.
Regards,
Wolfram
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