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    SubjectRe: change last level cache alignment on x86?
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    On Thu, 2012-03-01 at 16:33 +0800, Alex,Shi wrote:
    > Currently last level defined in kernel is still 128 bytes, but actually
    > I checked intel's core2, NHM, SNB, atom, serial platforms, all of them
    > are using 64 bytes.
    > I did not get detailed info on AMD platforms. Guess someone like to give
    > the info here. So, Is if it possible to do the similar following changes
    > to use 64 byte cache alignment in kernel?
    >
    > ===
    > diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
    > index 3c57033..f342a5a 100644
    > --- a/arch/x86/Kconfig.cpu
    > +++ b/arch/x86/Kconfig.cpu
    > @@ -303,7 +303,7 @@ config X86_GENERIC
    > config X86_INTERNODE_CACHE_SHIFT
    > int
    > default "12" if X86_VSMP
    > - default "7" if NUMA
    > + default "7" if NUMA && (MPENTIUM4)
    > default X86_L1_CACHE_SHIFT
    >
    > config X86_CMPXCHG

    In arch/x86/include/asm/cache.h, the INTERNODE_CACHE_SHIFT macro will
    transfer to '__cacheline_aligned_in_smp' finally.

    #ifdef CONFIG_X86_VSMP
    #ifdef CONFIG_SMP
    #define __cacheline_aligned_in_smp \
    __attribute__((__aligned__(INTERNODE_CACHE_BYTES))) \
    __page_aligned_data
    #endif
    #endif

    look at the following contents in Kconfig.cpu, I wondering if it is
    possible to remove 'default "7" if NUMA' line. Then a thin and fit cache
    alignment will be potential helpful on performance.
    Anyone like to give some comments?

    ===
    diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
    index 3c57033..6443c6f 100644
    --- a/arch/x86/Kconfig.cpu
    +++ b/arch/x86/Kconfig.cpu
    @@ -303,7 +303,6 @@ config X86_GENERIC
    config X86_INTERNODE_CACHE_SHIFT
    int
    default "12" if X86_VSMP
    - default "7" if NUMA
    default X86_L1_CACHE_SHIFT

    config X86_CMPXCHG
    ====
    some contents in Kconfig.cpu:

    config X86_INTERNODE_CACHE_SHIFT
    int
    default "12" if X86_VSMP
    default "7" if NUMA && (MPENTIUM4 || MPSC)
    default X86_L1_CACHE_SHIFT
    config X86_CMPXCHG
    def_bool X86_64 || (X86_32 && !M386)
    config X86_L1_CACHE_SHIFT
    int
    default "7" if MPENTIUM4 || MPSC
    default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
    default "4" if MELAN || M486 || M386 || MGEODEGX1
    default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX

    >




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