Messages in this thread | | | Subject | Re: [PATCH 09/24] PCI, powerpc: Register busn_res for root buses | From | Benjamin Herrenschmidt <> | Date | Fri, 10 Feb 2012 08:35:58 +1100 |
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On Thu, 2012-02-09 at 11:24 -0800, Bjorn Helgaas wrote: > My point is that the interface between the arch and the PCI core > should be simply the arch telling the core "this is the range of bus > numbers you can use." If the firmware doesn't give you the HW limits, > that's the arch's problem. If you want to assume 0..255 are > available, again, that's the arch's decision. > > But the answer to the question "what bus numbers are available to me" > depends only on the host bridge HW configuration. It does not depend > on what pci_scan_child_bus() found. Therefore, I think we can come up > with a design where pci_bus_update_busn_res_end() is unnecessary.
In an ideal world yes. In a world where there are reverse engineered platforms on which we aren't 100% sure how thing actually work under the hood and have the code just adapt on "what's there" (and try to fix it up -sometimes-), thinks can get a bit murky :-)
But yes, I see your point. As for what is the "correct" setting that needs to be done so that the patch doesn't end up a regression for us, I'll have to dig into some ancient HW to dbl check a few things. I hope 0...255 will just work but I can't guarantee it.
What I'll probably do is constraint the core to the values in hose->min/max, and update selected platforms to put 0..255 in there when I know for sure they can cope.
Cheers, Ben.
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