lkml.org 
[lkml]   [2012]   [Dec]   [6]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 2/6 v9] clk, highbank: Prevent glitches in non-bypass reset mode
    Date
    The highbank clock will glitch with the current code if the
    clock rate is reset without relocking the PLL. Program the PLL
    correctly to prevent glitches.

    Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
    Signed-off-by: Rob Herring <rob.herring@calxeda.com>
    Acked-by: Mike Turquette <mturquette@linaro.org>
    ---
    Changes from v6, v7, v8
    None.
    Changes from v5
    Added Mike Turquette's ack.
    Changes from v4
    None.
    Changes from v3
    Changelog text and patch name now correspond to the actual patch.
    was clk, highbank: remove non-bypass reset mode.
    Changes from v2
    None.
    Changes from v1
    Removed erroneous reformating.

    drivers/clk/clk-highbank.c | 2 ++
    1 file changed, 2 insertions(+)

    diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
    index 52fecad..3a0b723 100644
    --- a/drivers/clk/clk-highbank.c
    +++ b/drivers/clk/clk-highbank.c
    @@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
    reg |= HB_PLL_EXT_ENA;
    reg &= ~HB_PLL_EXT_BYPASS;
    } else {
    + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
    reg &= ~HB_PLL_DIVQ_MASK;
    reg |= divq << HB_PLL_DIVQ_SHIFT;
    + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
    }
    writel(reg, hbclk->reg);

    --
    1.7.11.7


    \
     
     \ /
      Last update: 2012-12-07 00:21    [W:2.488 / U:0.188 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site