Messages in this thread | | | Date | Fri, 12 Oct 2012 08:18:13 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH RFC 2/2] [x86] Optimize copy_page by re-arranging instruction sequence and saving register |
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On Fri, Oct 12, 2012 at 03:37:50AM +0000, Ma, Ling wrote: > > > Load and write operation occupy about 35% and 10% respectively for > > > most industry benchmarks. Fetched 16-aligned bytes code include about > > > 4 instructions, implying 1.34(0.35 * 4) load, 0.4 write. > > > Modern CPU support 2 load and 1 write per cycle, so throughput from > > > write is bottleneck for memcpy or copy_page, and some slight CPU only > > > support one mem operation per cycle. So it is enough to issue one > > read > > > and write instruction per cycle, and we can save registers. > > > > So is that also true for AMD CPUs? > Although Bulldozer put 32byte instruction into decoupled 16byte entry buffers, > it still decode 4 instructions per cycle, so 4 instructions will be fed into execution unit and > 2 loads ,1 write will be issued per cycle.
I'd be very interested with what benchmarks are you seeing that perf improvement on Atom and who knows, maybe I could find time to run them on Bulldozer and see how your patch behaves there :-).
Thanks.
-- Regards/Gruss, Boris.
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