Messages in this thread | | | Subject | Re: [PATCH] mtd: atmel_nand: fix access to 16 bit NAND devices | From | Artem Bityutskiy <> | Date | Fri, 27 Jan 2012 15:29:56 +0200 |
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On Wed, 2012-01-18 at 10:16 +0100, Nikolaus Voss wrote: > commit fb5427508abbd635e877fabdf55795488119c2d6 optimizes PIO > NAND accesses by using IO memcpy instead of IO read/write > repeated functions. > > This breaks access to 16 bit NAND devices as memcpy_fromio()/toio() > _always_ use byte accesses (see arch/arm/kernel/io.c), so with > 16 bit NAND, one byte gets lost per NAND access cycle and NAND > address count is wrong. > > Using memcpy() instead of the IO memcpy functions fixes this, but > depends on correct word alignment of the buffer and length has to > be a multiple of four, otherwise it might issue byte accesses and > possibly break 16 bit NAND access (cf arch/arm/lib/copy_template.S). > > Memcpy variants seem to be the wrong approach here, since the > NAND controller doesn't make the NAND appear as truely randomly > accessible memory (as opposed to the DRAM controller which does > exactly that). > > So, my proposal is to use 32 bit IO read/write (and let SMC > map it to 8 bit or 16 bit NAND accesses) and account for > length % 4 > 0 with two additional IO read/writes. > > Signed-off-by: Nikolaus Voss <n.voss@weinmann.de>
Why not to revert fb5427508abbd635e877fabdf55795488119c2d6 instead, it is in my opinion a bit more readable?
-- Best Regards, Artem Bityutskiy [unhandled content-type:application/pgp-signature] | |