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    SubjectRe: Workaround for Intel MPS errata
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    > Hey Avi,
    > Can you try this patch? It should resolve the issue you are seeing.
    >
    > Thanks,
    > Jon
    >
    > PCI: Workaround for Intel MPS errata
    >
    > Intel 5000 and 5100 series memory controllers have a known issue if
    > read
    > completion coalescing is enabled (the default setting) and the PCI-E
    > Maximum Payload Size is set to 256B. To work around this issue,
    > disable
    > read completion coalescing if the MPS is 256B.
    >
    > http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf
    > http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf
    >
    > Reported-by: Avi Kivity <avi@redhat.com>
    > Signed-off-by: Jon Mason <mason@myri.com>
    >
    > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
    > index a919db2..13c733a 100644
    > --- a/drivers/pci/probe.c
    > +++ b/drivers/pci/probe.c
    > @@ -1361,6 +1361,80 @@ static int pcie_find_smpss(struct pci_dev *dev,
    > void *data)
    > return 0;
    > }
    >
    > +static void pcie_errata_check(int mps)
    > +{

    While this whole function is about Intel 5x00 devices the name of it is
    very generic (and in a very generic file). Maybe this can be changed, e.g.
    "fixup:" renamed to "fixup_intel_5x00:". Also I wonder if that shouldn't
    be a nop when CONFIG_PCI_QUIRKS is not set.

    Eike


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