Messages in this thread | | | From | Chris Wilson <> | Subject | Re: PCH reference clock cleanups | Date | Tue, 27 Sep 2011 10:01:33 +0100 |
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On Mon, 26 Sep 2011 23:11:37 -0700, Keith Packard <keithp@keithp.com> wrote: > Ok, so I'd love to know where in any PCH reference matter someone has > found a place where the reference clock for any of the PLLs is > anything other than 120MHz. Can someone find a reference for other frequencies?
Oddly in the diagram SSC4 is given as a 100MHz clock that can be used for any output other than DP_A. However, the configuration register marks that as being a test-only mode. -Chris
-- Chris Wilson, Intel Open Source Technology Centre
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