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    Subject[PATCH v4 07/19] Staging: cx25821: Fix wrong statement indent in cx25821-core.c
    Date
    Fix wrong brace placement and statement indent in cx25821-core.c

    Signed-off-by: Leonid V. Fedorenchik <leonidsbox@gmail.com>
    ---
    drivers/staging/cx25821/cx25821-core.c | 500 ++++++++++++++++----------------
    1 files changed, 250 insertions(+), 250 deletions(-)

    diff --git a/drivers/staging/cx25821/cx25821-core.c b/drivers/staging/cx25821/cx25821-core.c
    index 26d2879..3ec58af 100644
    --- a/drivers/staging/cx25821/cx25821-core.c
    +++ b/drivers/staging/cx25821/cx25821-core.c
    @@ -50,270 +50,270 @@ EXPORT_SYMBOL(cx25821_devlist);

    struct sram_channel cx25821_sram_channels[] = {
    [SRAM_CH00] = {
    - .i = SRAM_CH00,
    - .name = "VID A",
    - .cmds_start = VID_A_DOWN_CMDS,
    - .ctrl_start = VID_A_IQ,
    - .cdt = VID_A_CDT,
    - .fifo_start = VID_A_DOWN_CLUSTER_1,
    - .fifo_size = (VID_CLUSTER_SIZE << 2),
    - .ptr1_reg = DMA1_PTR1,
    - .ptr2_reg = DMA1_PTR2,
    - .cnt1_reg = DMA1_CNT1,
    - .cnt2_reg = DMA1_CNT2,
    - .int_msk = VID_A_INT_MSK,
    - .int_stat = VID_A_INT_STAT,
    - .int_mstat = VID_A_INT_MSTAT,
    - .dma_ctl = VID_DST_A_DMA_CTL,
    - .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
    - .gpcnt = VID_DST_A_GPCNT,
    - .vip_ctl = VID_DST_A_VIP_CTL,
    - .pix_frmt = VID_DST_A_PIX_FRMT,
    - },
    + .i = SRAM_CH00,
    + .name = "VID A",
    + .cmds_start = VID_A_DOWN_CMDS,
    + .ctrl_start = VID_A_IQ,
    + .cdt = VID_A_CDT,
    + .fifo_start = VID_A_DOWN_CLUSTER_1,
    + .fifo_size = (VID_CLUSTER_SIZE << 2),
    + .ptr1_reg = DMA1_PTR1,
    + .ptr2_reg = DMA1_PTR2,
    + .cnt1_reg = DMA1_CNT1,
    + .cnt2_reg = DMA1_CNT2,
    + .int_msk = VID_A_INT_MSK,
    + .int_stat = VID_A_INT_STAT,
    + .int_mstat = VID_A_INT_MSTAT,
    + .dma_ctl = VID_DST_A_DMA_CTL,
    + .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
    + .gpcnt = VID_DST_A_GPCNT,
    + .vip_ctl = VID_DST_A_VIP_CTL,
    + .pix_frmt = VID_DST_A_PIX_FRMT,
    + },

    [SRAM_CH01] = {
    - .i = SRAM_CH01,
    - .name = "VID B",
    - .cmds_start = VID_B_DOWN_CMDS,
    - .ctrl_start = VID_B_IQ,
    - .cdt = VID_B_CDT,
    - .fifo_start = VID_B_DOWN_CLUSTER_1,
    - .fifo_size = (VID_CLUSTER_SIZE << 2),
    - .ptr1_reg = DMA2_PTR1,
    - .ptr2_reg = DMA2_PTR2,
    - .cnt1_reg = DMA2_CNT1,
    - .cnt2_reg = DMA2_CNT2,
    - .int_msk = VID_B_INT_MSK,
    - .int_stat = VID_B_INT_STAT,
    - .int_mstat = VID_B_INT_MSTAT,
    - .dma_ctl = VID_DST_B_DMA_CTL,
    - .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
    - .gpcnt = VID_DST_B_GPCNT,
    - .vip_ctl = VID_DST_B_VIP_CTL,
    - .pix_frmt = VID_DST_B_PIX_FRMT,
    - },
    + .i = SRAM_CH01,
    + .name = "VID B",
    + .cmds_start = VID_B_DOWN_CMDS,
    + .ctrl_start = VID_B_IQ,
    + .cdt = VID_B_CDT,
    + .fifo_start = VID_B_DOWN_CLUSTER_1,
    + .fifo_size = (VID_CLUSTER_SIZE << 2),
    + .ptr1_reg = DMA2_PTR1,
    + .ptr2_reg = DMA2_PTR2,
    + .cnt1_reg = DMA2_CNT1,
    + .cnt2_reg = DMA2_CNT2,
    + .int_msk = VID_B_INT_MSK,
    + .int_stat = VID_B_INT_STAT,
    + .int_mstat = VID_B_INT_MSTAT,
    + .dma_ctl = VID_DST_B_DMA_CTL,
    + .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
    + .gpcnt = VID_DST_B_GPCNT,
    + .vip_ctl = VID_DST_B_VIP_CTL,
    + .pix_frmt = VID_DST_B_PIX_FRMT,
    + },

    [SRAM_CH02] = {
    - .i = SRAM_CH02,
    - .name = "VID C",
    - .cmds_start = VID_C_DOWN_CMDS,
    - .ctrl_start = VID_C_IQ,
    - .cdt = VID_C_CDT,
    - .fifo_start = VID_C_DOWN_CLUSTER_1,
    - .fifo_size = (VID_CLUSTER_SIZE << 2),
    - .ptr1_reg = DMA3_PTR1,
    - .ptr2_reg = DMA3_PTR2,
    - .cnt1_reg = DMA3_CNT1,
    - .cnt2_reg = DMA3_CNT2,
    - .int_msk = VID_C_INT_MSK,
    - .int_stat = VID_C_INT_STAT,
    - .int_mstat = VID_C_INT_MSTAT,
    - .dma_ctl = VID_DST_C_DMA_CTL,
    - .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
    - .gpcnt = VID_DST_C_GPCNT,
    - .vip_ctl = VID_DST_C_VIP_CTL,
    - .pix_frmt = VID_DST_C_PIX_FRMT,
    - },
    + .i = SRAM_CH02,
    + .name = "VID C",
    + .cmds_start = VID_C_DOWN_CMDS,
    + .ctrl_start = VID_C_IQ,
    + .cdt = VID_C_CDT,
    + .fifo_start = VID_C_DOWN_CLUSTER_1,
    + .fifo_size = (VID_CLUSTER_SIZE << 2),
    + .ptr1_reg = DMA3_PTR1,
    + .ptr2_reg = DMA3_PTR2,
    + .cnt1_reg = DMA3_CNT1,
    + .cnt2_reg = DMA3_CNT2,
    + .int_msk = VID_C_INT_MSK,
    + .int_stat = VID_C_INT_STAT,
    + .int_mstat = VID_C_INT_MSTAT,
    + .dma_ctl = VID_DST_C_DMA_CTL,
    + .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
    + .gpcnt = VID_DST_C_GPCNT,
    + .vip_ctl = VID_DST_C_VIP_CTL,
    + .pix_frmt = VID_DST_C_PIX_FRMT,
    + },

    [SRAM_CH03] = {
    - .i = SRAM_CH03,
    - .name = "VID D",
    - .cmds_start = VID_D_DOWN_CMDS,
    - .ctrl_start = VID_D_IQ,
    - .cdt = VID_D_CDT,
    - .fifo_start = VID_D_DOWN_CLUSTER_1,
    - .fifo_size = (VID_CLUSTER_SIZE << 2),
    - .ptr1_reg = DMA4_PTR1,
    - .ptr2_reg = DMA4_PTR2,
    - .cnt1_reg = DMA4_CNT1,
    - .cnt2_reg = DMA4_CNT2,
    - .int_msk = VID_D_INT_MSK,
    - .int_stat = VID_D_INT_STAT,
    - .int_mstat = VID_D_INT_MSTAT,
    - .dma_ctl = VID_DST_D_DMA_CTL,
    - .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
    - .gpcnt = VID_DST_D_GPCNT,
    - .vip_ctl = VID_DST_D_VIP_CTL,
    - .pix_frmt = VID_DST_D_PIX_FRMT,
    - },
    + .i = SRAM_CH03,
    + .name = "VID D",
    + .cmds_start = VID_D_DOWN_CMDS,
    + .ctrl_start = VID_D_IQ,
    + .cdt = VID_D_CDT,
    + .fifo_start = VID_D_DOWN_CLUSTER_1,
    + .fifo_size = (VID_CLUSTER_SIZE << 2),
    + .ptr1_reg = DMA4_PTR1,
    + .ptr2_reg = DMA4_PTR2,
    + .cnt1_reg = DMA4_CNT1,
    + .cnt2_reg = DMA4_CNT2,
    + .int_msk = VID_D_INT_MSK,
    + .int_stat = VID_D_INT_STAT,
    + .int_mstat = VID_D_INT_MSTAT,
    + .dma_ctl = VID_DST_D_DMA_CTL,
    + .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
    + .gpcnt = VID_DST_D_GPCNT,
    + .vip_ctl = VID_DST_D_VIP_CTL,
    + .pix_frmt = VID_DST_D_PIX_FRMT,
    + },

    [SRAM_CH04] = {
    - .i = SRAM_CH04,
    - .name = "VID E",
    - .cmds_start = VID_E_DOWN_CMDS,
    - .ctrl_start = VID_E_IQ,
    - .cdt = VID_E_CDT,
    - .fifo_start = VID_E_DOWN_CLUSTER_1,
    - .fifo_size = (VID_CLUSTER_SIZE << 2),
    - .ptr1_reg = DMA5_PTR1,
    - .ptr2_reg = DMA5_PTR2,
    - .cnt1_reg = DMA5_CNT1,
    - .cnt2_reg = DMA5_CNT2,
    - .int_msk = VID_E_INT_MSK,
    - .int_stat = VID_E_INT_STAT,
    - .int_mstat = VID_E_INT_MSTAT,
    - .dma_ctl = VID_DST_E_DMA_CTL,
    - .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
    - .gpcnt = VID_DST_E_GPCNT,
    - .vip_ctl = VID_DST_E_VIP_CTL,
    - .pix_frmt = VID_DST_E_PIX_FRMT,
    - },
    + .i = SRAM_CH04,
    + .name = "VID E",
    + .cmds_start = VID_E_DOWN_CMDS,
    + .ctrl_start = VID_E_IQ,
    + .cdt = VID_E_CDT,
    + .fifo_start = VID_E_DOWN_CLUSTER_1,
    + .fifo_size = (VID_CLUSTER_SIZE << 2),
    + .ptr1_reg = DMA5_PTR1,
    + .ptr2_reg = DMA5_PTR2,
    + .cnt1_reg = DMA5_CNT1,
    + .cnt2_reg = DMA5_CNT2,
    + .int_msk = VID_E_INT_MSK,
    + .int_stat = VID_E_INT_STAT,
    + .int_mstat = VID_E_INT_MSTAT,
    + .dma_ctl = VID_DST_E_DMA_CTL,
    + .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
    + .gpcnt = VID_DST_E_GPCNT,
    + .vip_ctl = VID_DST_E_VIP_CTL,
    + .pix_frmt = VID_DST_E_PIX_FRMT,
    + },

    [SRAM_CH05] = {
    - .i = SRAM_CH05,
    - .name = "VID F",
    - .cmds_start = VID_F_DOWN_CMDS,
    - .ctrl_start = VID_F_IQ,
    - .cdt = VID_F_CDT,
    - .fifo_start = VID_F_DOWN_CLUSTER_1,
    - .fifo_size = (VID_CLUSTER_SIZE << 2),
    - .ptr1_reg = DMA6_PTR1,
    - .ptr2_reg = DMA6_PTR2,
    - .cnt1_reg = DMA6_CNT1,
    - .cnt2_reg = DMA6_CNT2,
    - .int_msk = VID_F_INT_MSK,
    - .int_stat = VID_F_INT_STAT,
    - .int_mstat = VID_F_INT_MSTAT,
    - .dma_ctl = VID_DST_F_DMA_CTL,
    - .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
    - .gpcnt = VID_DST_F_GPCNT,
    - .vip_ctl = VID_DST_F_VIP_CTL,
    - .pix_frmt = VID_DST_F_PIX_FRMT,
    - },
    + .i = SRAM_CH05,
    + .name = "VID F",
    + .cmds_start = VID_F_DOWN_CMDS,
    + .ctrl_start = VID_F_IQ,
    + .cdt = VID_F_CDT,
    + .fifo_start = VID_F_DOWN_CLUSTER_1,
    + .fifo_size = (VID_CLUSTER_SIZE << 2),
    + .ptr1_reg = DMA6_PTR1,
    + .ptr2_reg = DMA6_PTR2,
    + .cnt1_reg = DMA6_CNT1,
    + .cnt2_reg = DMA6_CNT2,
    + .int_msk = VID_F_INT_MSK,
    + .int_stat = VID_F_INT_STAT,
    + .int_mstat = VID_F_INT_MSTAT,
    + .dma_ctl = VID_DST_F_DMA_CTL,
    + .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
    + .gpcnt = VID_DST_F_GPCNT,
    + .vip_ctl = VID_DST_F_VIP_CTL,
    + .pix_frmt = VID_DST_F_PIX_FRMT,
    + },

    [SRAM_CH06] = {
    - .i = SRAM_CH06,
    - .name = "VID G",
    - .cmds_start = VID_G_DOWN_CMDS,
    - .ctrl_start = VID_G_IQ,
    - .cdt = VID_G_CDT,
    - .fifo_start = VID_G_DOWN_CLUSTER_1,
    - .fifo_size = (VID_CLUSTER_SIZE << 2),
    - .ptr1_reg = DMA7_PTR1,
    - .ptr2_reg = DMA7_PTR2,
    - .cnt1_reg = DMA7_CNT1,
    - .cnt2_reg = DMA7_CNT2,
    - .int_msk = VID_G_INT_MSK,
    - .int_stat = VID_G_INT_STAT,
    - .int_mstat = VID_G_INT_MSTAT,
    - .dma_ctl = VID_DST_G_DMA_CTL,
    - .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
    - .gpcnt = VID_DST_G_GPCNT,
    - .vip_ctl = VID_DST_G_VIP_CTL,
    - .pix_frmt = VID_DST_G_PIX_FRMT,
    - },
    + .i = SRAM_CH06,
    + .name = "VID G",
    + .cmds_start = VID_G_DOWN_CMDS,
    + .ctrl_start = VID_G_IQ,
    + .cdt = VID_G_CDT,
    + .fifo_start = VID_G_DOWN_CLUSTER_1,
    + .fifo_size = (VID_CLUSTER_SIZE << 2),
    + .ptr1_reg = DMA7_PTR1,
    + .ptr2_reg = DMA7_PTR2,
    + .cnt1_reg = DMA7_CNT1,
    + .cnt2_reg = DMA7_CNT2,
    + .int_msk = VID_G_INT_MSK,
    + .int_stat = VID_G_INT_STAT,
    + .int_mstat = VID_G_INT_MSTAT,
    + .dma_ctl = VID_DST_G_DMA_CTL,
    + .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
    + .gpcnt = VID_DST_G_GPCNT,
    + .vip_ctl = VID_DST_G_VIP_CTL,
    + .pix_frmt = VID_DST_G_PIX_FRMT,
    + },

    [SRAM_CH07] = {
    - .i = SRAM_CH07,
    - .name = "VID H",
    - .cmds_start = VID_H_DOWN_CMDS,
    - .ctrl_start = VID_H_IQ,
    - .cdt = VID_H_CDT,
    - .fifo_start = VID_H_DOWN_CLUSTER_1,
    - .fifo_size = (VID_CLUSTER_SIZE << 2),
    - .ptr1_reg = DMA8_PTR1,
    - .ptr2_reg = DMA8_PTR2,
    - .cnt1_reg = DMA8_CNT1,
    - .cnt2_reg = DMA8_CNT2,
    - .int_msk = VID_H_INT_MSK,
    - .int_stat = VID_H_INT_STAT,
    - .int_mstat = VID_H_INT_MSTAT,
    - .dma_ctl = VID_DST_H_DMA_CTL,
    - .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
    - .gpcnt = VID_DST_H_GPCNT,
    - .vip_ctl = VID_DST_H_VIP_CTL,
    - .pix_frmt = VID_DST_H_PIX_FRMT,
    - },
    + .i = SRAM_CH07,
    + .name = "VID H",
    + .cmds_start = VID_H_DOWN_CMDS,
    + .ctrl_start = VID_H_IQ,
    + .cdt = VID_H_CDT,
    + .fifo_start = VID_H_DOWN_CLUSTER_1,
    + .fifo_size = (VID_CLUSTER_SIZE << 2),
    + .ptr1_reg = DMA8_PTR1,
    + .ptr2_reg = DMA8_PTR2,
    + .cnt1_reg = DMA8_CNT1,
    + .cnt2_reg = DMA8_CNT2,
    + .int_msk = VID_H_INT_MSK,
    + .int_stat = VID_H_INT_STAT,
    + .int_mstat = VID_H_INT_MSTAT,
    + .dma_ctl = VID_DST_H_DMA_CTL,
    + .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
    + .gpcnt = VID_DST_H_GPCNT,
    + .vip_ctl = VID_DST_H_VIP_CTL,
    + .pix_frmt = VID_DST_H_PIX_FRMT,
    + },

    [SRAM_CH08] = {
    - .name = "audio from",
    - .cmds_start = AUD_A_DOWN_CMDS,
    - .ctrl_start = AUD_A_IQ,
    - .cdt = AUD_A_CDT,
    - .fifo_start = AUD_A_DOWN_CLUSTER_1,
    - .fifo_size = AUDIO_CLUSTER_SIZE * 3,
    - .ptr1_reg = DMA17_PTR1,
    - .ptr2_reg = DMA17_PTR2,
    - .cnt1_reg = DMA17_CNT1,
    - .cnt2_reg = DMA17_CNT2,
    - },
    + .name = "audio from",
    + .cmds_start = AUD_A_DOWN_CMDS,
    + .ctrl_start = AUD_A_IQ,
    + .cdt = AUD_A_CDT,
    + .fifo_start = AUD_A_DOWN_CLUSTER_1,
    + .fifo_size = AUDIO_CLUSTER_SIZE * 3,
    + .ptr1_reg = DMA17_PTR1,
    + .ptr2_reg = DMA17_PTR2,
    + .cnt1_reg = DMA17_CNT1,
    + .cnt2_reg = DMA17_CNT2,
    + },

    [SRAM_CH09] = {
    - .i = SRAM_CH09,
    - .name = "VID Upstream I",
    - .cmds_start = VID_I_UP_CMDS,
    - .ctrl_start = VID_I_IQ,
    - .cdt = VID_I_CDT,
    - .fifo_start = VID_I_UP_CLUSTER_1,
    - .fifo_size = (VID_CLUSTER_SIZE << 2),
    - .ptr1_reg = DMA15_PTR1,
    - .ptr2_reg = DMA15_PTR2,
    - .cnt1_reg = DMA15_CNT1,
    - .cnt2_reg = DMA15_CNT2,
    - .int_msk = VID_I_INT_MSK,
    - .int_stat = VID_I_INT_STAT,
    - .int_mstat = VID_I_INT_MSTAT,
    - .dma_ctl = VID_SRC_I_DMA_CTL,
    - .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
    - .gpcnt = VID_SRC_I_GPCNT,
    -
    - .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
    - .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
    - .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
    - .vid_cdt_size = VID_SRC_I_CDT_SZ,
    - .irq_bit = 8,
    - },
    + .i = SRAM_CH09,
    + .name = "VID Upstream I",
    + .cmds_start = VID_I_UP_CMDS,
    + .ctrl_start = VID_I_IQ,
    + .cdt = VID_I_CDT,
    + .fifo_start = VID_I_UP_CLUSTER_1,
    + .fifo_size = (VID_CLUSTER_SIZE << 2),
    + .ptr1_reg = DMA15_PTR1,
    + .ptr2_reg = DMA15_PTR2,
    + .cnt1_reg = DMA15_CNT1,
    + .cnt2_reg = DMA15_CNT2,
    + .int_msk = VID_I_INT_MSK,
    + .int_stat = VID_I_INT_STAT,
    + .int_mstat = VID_I_INT_MSTAT,
    + .dma_ctl = VID_SRC_I_DMA_CTL,
    + .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
    + .gpcnt = VID_SRC_I_GPCNT,
    +
    + .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
    + .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
    + .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
    + .vid_cdt_size = VID_SRC_I_CDT_SZ,
    + .irq_bit = 8,
    + },

    [SRAM_CH10] = {
    - .i = SRAM_CH10,
    - .name = "VID Upstream J",
    - .cmds_start = VID_J_UP_CMDS,
    - .ctrl_start = VID_J_IQ,
    - .cdt = VID_J_CDT,
    - .fifo_start = VID_J_UP_CLUSTER_1,
    - .fifo_size = (VID_CLUSTER_SIZE << 2),
    - .ptr1_reg = DMA16_PTR1,
    - .ptr2_reg = DMA16_PTR2,
    - .cnt1_reg = DMA16_CNT1,
    - .cnt2_reg = DMA16_CNT2,
    - .int_msk = VID_J_INT_MSK,
    - .int_stat = VID_J_INT_STAT,
    - .int_mstat = VID_J_INT_MSTAT,
    - .dma_ctl = VID_SRC_J_DMA_CTL,
    - .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
    - .gpcnt = VID_SRC_J_GPCNT,
    -
    - .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
    - .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
    - .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
    - .vid_cdt_size = VID_SRC_J_CDT_SZ,
    - .irq_bit = 9,
    - },
    + .i = SRAM_CH10,
    + .name = "VID Upstream J",
    + .cmds_start = VID_J_UP_CMDS,
    + .ctrl_start = VID_J_IQ,
    + .cdt = VID_J_CDT,
    + .fifo_start = VID_J_UP_CLUSTER_1,
    + .fifo_size = (VID_CLUSTER_SIZE << 2),
    + .ptr1_reg = DMA16_PTR1,
    + .ptr2_reg = DMA16_PTR2,
    + .cnt1_reg = DMA16_CNT1,
    + .cnt2_reg = DMA16_CNT2,
    + .int_msk = VID_J_INT_MSK,
    + .int_stat = VID_J_INT_STAT,
    + .int_mstat = VID_J_INT_MSTAT,
    + .dma_ctl = VID_SRC_J_DMA_CTL,
    + .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
    + .gpcnt = VID_SRC_J_GPCNT,
    +
    + .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
    + .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
    + .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
    + .vid_cdt_size = VID_SRC_J_CDT_SZ,
    + .irq_bit = 9,
    + },

    [SRAM_CH11] = {
    - .i = SRAM_CH11,
    - .name = "Audio Upstream Channel B",
    - .cmds_start = AUD_B_UP_CMDS,
    - .ctrl_start = AUD_B_IQ,
    - .cdt = AUD_B_CDT,
    - .fifo_start = AUD_B_UP_CLUSTER_1,
    - .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
    - .ptr1_reg = DMA22_PTR1,
    - .ptr2_reg = DMA22_PTR2,
    - .cnt1_reg = DMA22_CNT1,
    - .cnt2_reg = DMA22_CNT2,
    - .int_msk = AUD_B_INT_MSK,
    - .int_stat = AUD_B_INT_STAT,
    - .int_mstat = AUD_B_INT_MSTAT,
    - .dma_ctl = AUD_INT_DMA_CTL,
    - .gpcnt_ctl = AUD_B_GPCNT_CTL,
    - .gpcnt = AUD_B_GPCNT,
    - .aud_length = AUD_B_LNGTH,
    - .aud_cfg = AUD_B_CFG,
    - .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
    - .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
    - .irq_bit = 11,
    - },
    + .i = SRAM_CH11,
    + .name = "Audio Upstream Channel B",
    + .cmds_start = AUD_B_UP_CMDS,
    + .ctrl_start = AUD_B_IQ,
    + .cdt = AUD_B_CDT,
    + .fifo_start = AUD_B_UP_CLUSTER_1,
    + .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
    + .ptr1_reg = DMA22_PTR1,
    + .ptr2_reg = DMA22_PTR2,
    + .cnt1_reg = DMA22_CNT1,
    + .cnt2_reg = DMA22_CNT2,
    + .int_msk = AUD_B_INT_MSK,
    + .int_stat = AUD_B_INT_STAT,
    + .int_mstat = AUD_B_INT_MSTAT,
    + .dma_ctl = AUD_INT_DMA_CTL,
    + .gpcnt_ctl = AUD_B_GPCNT_CTL,
    + .gpcnt = AUD_B_GPCNT,
    + .aud_length = AUD_B_LNGTH,
    + .aud_cfg = AUD_B_CFG,
    + .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
    + .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
    + .irq_bit = 11,
    + },
    };
    EXPORT_SYMBOL(cx25821_sram_channels);

    @@ -1475,15 +1475,15 @@ static void __devexit cx25821_finidev(struct pci_dev *pci_dev)

    static DEFINE_PCI_DEVICE_TABLE(cx25821_pci_tbl) = {
    {
    - /* CX25821 Athena */
    - .vendor = 0x14f1,
    - .device = 0x8210,
    - .subvendor = 0x14f1,
    - .subdevice = 0x0920,
    - },
    + /* CX25821 Athena */
    + .vendor = 0x14f1,
    + .device = 0x8210,
    + .subvendor = 0x14f1,
    + .subdevice = 0x0920,
    + },
    {
    - /* --- end of list --- */
    - }
    + /* --- end of list --- */
    + }
    };

    MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
    --
    1.7.0.4


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