Messages in this thread | | | Date | Mon, 29 Aug 2011 10:40:03 +0200 | Subject | Re: [PATCH 1/4 v4] drivers: create a pin control subsystem | From | Linus Walleij <> |
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On Fri, Aug 26, 2011 at 7:33 PM, Stephen Warren <swarren@nvidia.com> wrote:
> However, we'd then need a extra table defining what each locality meant: > > function locality list_of_pins_in_function_at_locality > -------- -------- ------------------------------------ > i2c0 0 0, 1 > i2c0 1 2, 3 > (hard-coded into pinmux driver implementation)
I *think* this is what I have implemented in the v5 patch set, have a look.
> It seems slightly more complex to me to have these two separate tables, > rather than just iterating over n entries in a single mapping table.
I can deal with it....
> Still, I suppose this an implementation detail. I guess I also need to > think a little more about how both those models would work with Tegra, > where special functions are selected at a granularity of pin groups, > yet GPIO is selected at a granularity of a single pin. Perhaps that > final table I wrote above (mapping locality to pin list) might also help > represent Tegra's pin-group- rather than pin-level muxing capabilities...
I have made the assumption that we want to handle groups of pins, so a certain function in a certain position represents what the device want to request.
Well, let's look at the code...
Thanks, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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