Messages in this thread | | | Date | Fri, 12 Aug 2011 20:07:47 +0200 | From | Robert Richter <> | Subject | Re: [PATCH 4/7] perf, x86: Implement IBS interrupt handler |
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On 02.08.11 07:43:28, Peter Zijlstra wrote: > On Thu, 2011-07-28 at 15:46 +0200, Robert Richter wrote: > > + msr = hwc->config_base; > > + buf = buffer; > > + rdmsrl(msr++, *buf); > > + if (!(*buf++ & perf_ibs->valid_mask)) > > + return 0; > > + > > + perf_sample_data_init(&data, 0); > > + if (event->attr.sample_type & PERF_SAMPLE_RAW) { > > + for (i = 1; i < perf_ibs->reg_count; i++) > > + rdmsrl(msr++, *buf++); > > + raw.size = sizeof(u32) + sizeof(u64) * perf_ibs->reg_count; > > + raw.data = buffer; > > + data.raw = &raw; > > + } > > OK, so this dumps a linear range of MSRs into the raw data buffer. The > only 'problem' I have with that is that Fam12 will then also dump 103A > IBS Control Register, which seems pointless.
I will implement a bit mask instead. We can then use for_each_set_bit() etc.
-Robert
-- Advanced Micro Devices, Inc. Operating System Research Center
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