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Subject[026/107] drm/i915: Fix gen6 (SNB) missed BLT ring interrupts.
2.6.39-stable review patch.  If anyone has any objections, please let us know.


From: Daniel J Blueman <>

commit 498e720b96379d8ee9c294950a01534a73defcf3 upstream.

The failure appeared in dmesg as:

[drm:i915_hangcheck_ring_idle] *ERROR* Hangcheck timer elapsed... blt
ring idle [waiting on 35064155, at 35064155], missed IRQ?

This works around that problem on by making the blitter command
streamer write interrupt state to the Hardware Status Page when a
MI_USER_INTERRUPT command is decoded, which appears to force the seqno
out to memory before the interrupt happens.

v1->v2: Moved to prior interrupt handler installation and RMW flags as
per feedback.
v2->v3: Removed RMW of flags (by anholt)

Signed-off-by: Daniel J Blueman <>
Signed-off-by: Eric Anholt <>
Tested-by: Chris Wilson <> [v1]
Tested-by: Eric Anholt <> [v1,v3]
(incidence of the bug with a testcase went from avg 2/1000 to
0/12651 in the latest test run (plus more for v1))
Tested-by: Kenneth Graunke <> [v1]
Tested-by: Robert Hooker <> [v1]
Signed-off-by: Dave Airlie <>
Signed-off-by: Greg Kroah-Hartman <>

drivers/gpu/drm/i915/i915_irq.c | 10 ++++++++++
1 file changed, 10 insertions(+)

--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1567,6 +1567,16 @@ static void ironlake_irq_preinstall(stru
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

I915_WRITE(HWSTAM, 0xeffe);
+ if (IS_GEN6(dev)) {
+ /* Workaround stalls observed on Sandy Bridge GPUs by
+ * making the blitter command streamer generate a
+ * write to the Hardware Status Page for
+ * MI_USER_INTERRUPT. This appears to serialize the
+ * previous seqno write out before the interrupt
+ * happens.
+ */
+ }

/* XXX hotplug from PCH */

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