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    SubjectRe: [PATCH] x86, AMD: Correct F15h IC aliasing issue
    On 07/22/2011 04:15 PM, Borislav Petkov wrote:
    > From: Borislav Petkov<>
    > This patch provides performance tuning for the "Bulldozer" CPU. With its
    > shared instruction cache there is a chance of generating an excessive
    > number of cache cross-invalidates when running specific workloads on the
    > cores of a compute module.
    > This excessive amount of cross-invalidations can be observed if cache
    > lines backed by shared physical memory alias in bits [14:12] of their
    > virtual addresses, as those bits are used for the index generation.
    > This patch addresses the issue by zeroing out the slice [14:12] of
    > the file mapping's virtual address at generation time, thus forcing
    > those bits the same for all mappings of a single shared library across
    > processes and, in doing so, avoids instruction cache aliases.
    > It also adds the kernel command line option
    > "unalias_va_addr=(32|64|off)" with which virtual address unaliasing
    > can be enabled for 32-bit or 64-bit x86 individually, or be completely
    > disabled.
    > This change leaves virtual region address allocation on other families
    > and/or vendors unaffected.

    Is it possible to derive the bit positions (and the need to mask them)
    from the cpuid description of the cache topology and sizes?

    error compiling committee.c: too many arguments to function

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      Last update: 2011-07-26 20:03    [W:0.022 / U:22.620 seconds]
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