Messages in this thread | | | Date | Tue, 26 Jul 2011 20:59:04 +0300 | From | Avi Kivity <> | Subject | Re: [PATCH] x86, AMD: Correct F15h IC aliasing issue |
| |
On 07/22/2011 04:15 PM, Borislav Petkov wrote: > From: Borislav Petkov<borislav.petkov@amd.com> > > This patch provides performance tuning for the "Bulldozer" CPU. With its > shared instruction cache there is a chance of generating an excessive > number of cache cross-invalidates when running specific workloads on the > cores of a compute module. > > This excessive amount of cross-invalidations can be observed if cache > lines backed by shared physical memory alias in bits [14:12] of their > virtual addresses, as those bits are used for the index generation. > > This patch addresses the issue by zeroing out the slice [14:12] of > the file mapping's virtual address at generation time, thus forcing > those bits the same for all mappings of a single shared library across > processes and, in doing so, avoids instruction cache aliases. > > It also adds the kernel command line option > "unalias_va_addr=(32|64|off)" with which virtual address unaliasing > can be enabled for 32-bit or 64-bit x86 individually, or be completely > disabled. > > This change leaves virtual region address allocation on other families > and/or vendors unaffected. >
Is it possible to derive the bit positions (and the need to mask them) from the cpuid description of the cache topology and sizes?
-- error compiling committee.c: too many arguments to function
| |