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    Subject[132/146] ARM: 6941/1: cache: ensure MVA is cacheline aligned in
    2.6.38-stable review patch.  If anyone has any objections, please let us know.


    From: Will Deacon <>

    commit a248b13b21ae00b97638b4f435c8df3075808b5d upstream.

    The v6 and v7 implementations of flush_kern_dcache_area do not align
    the passed MVA to the size of a cacheline in the data cache. If a
    misaligned address is used, only a subset of the requested area will
    be flushed. This has been observed to cause failures in SMP boot where
    the secondary_data initialised by the primary CPU is not cacheline
    aligned, causing the secondary CPUs to read incorrect values for their
    pgd and stack pointers.

    This patch ensures that the base address is cacheline aligned before
    flushing the d-cache.

    Acked-by: Catalin Marinas <>
    Signed-off-by: Will Deacon <>
    Signed-off-by: Russell King <>
    Signed-off-by: Greg Kroah-Hartman <>

    arch/arm/mm/cache-v6.S | 1 +
    arch/arm/mm/cache-v7.S | 2 ++
    2 files changed, 3 insertions(+)

    --- a/arch/arm/mm/cache-v6.S
    +++ b/arch/arm/mm/cache-v6.S
    @@ -176,6 +176,7 @@ ENDPROC(v6_coherent_kern_range)
    add r1, r0, r1
    + bic r0, r0, #D_CACHE_LINE_SIZE - 1
    #ifdef HARVARD_CACHE
    mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
    --- a/arch/arm/mm/cache-v7.S
    +++ b/arch/arm/mm/cache-v7.S
    @@ -221,6 +221,8 @@ ENDPROC(v7_coherent_user_range)
    dcache_line_size r2, r3
    add r1, r0, r1
    + sub r3, r2, #1
    + bic r0, r0, r3
    mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
    add r0, r0, r2

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