Messages in this thread | | | Subject | Re: [PATCH v5 02/19] ARM: LPAE: add ISBs around MMU enabling code | From | Catalin Marinas <> | Date | Mon, 09 May 2011 16:38:50 +0100 |
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On Mon, 2011-05-09 at 16:34 +0100, Russell King - ARM Linux wrote: > On Mon, May 09, 2011 at 04:01:56PM +0100, Catalin Marinas wrote: > > This doesn't work. From the ARM ARM (B1.3.3): > > > > The execution state bits are the IT[7:0], J, E, and T bits. In > > exception modes you can read or write these bits in the current > > SPSR. > > In the CPSR, unless the processor is in Debug state: > > • The execution state bits, other than the E bit, are RAZ when > > read by an MRS instruction. > > > > So reading the CPSR doesn't copy the T and E bits. Of course, we could > > set them explicitly but I find the ISB much simpler (and in practice we > > only need it for ARMv7 onwards but adding the ARMv6 in case we have a > > kernel compiled for both). > > Err. If that's correct then the Linux kernel is totally broken, and > that's an incompatible change to the behaviour of the MRS and MSR > instructions which has gone unnoticed. > > We use "MRS reg, cpsr" for saving the IRQ state in SVC mode and > "MSR cpsr, reg" to restore the interrupt state. If the T bit gets > reset by that, then Thumb kernels can never work. > > What you've just said tells me that our implementation of: > - arch_local_irq_save() > - arch_local_save_flags() > - arch_local_irq_restore() > won't work because we can't read or write the I and F bits using > MSR/MRS, even in SVC mode.
You can't write the execution state bits: IT[7:0], E and T.
You can write mask bits A, I and F using MSR.
> What is the replacement method for doing this?
For changing the execution state - SETEND, BX etc.
-- Catalin
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