Messages in this thread | | | Subject | Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events | From | Lin Ming <> | Date | Fri, 06 May 2011 21:47:47 +0800 |
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On Fri, 2011-05-06 at 17:19 +0800, Ingo Molnar wrote: > Btw., there's another missing Intel SandyBridge related perf events feature as > well which was not implemented with the Intel offcore bits. > > Peter did a raw first cut - entirely untested, see it below. Would you be > interested in testing it on Intel SandyBridge hw and sending (the working > version) to lkml with your Signed-off-by if the events looks good to you in > some real tests (i.e. are counting real LL cache events)?
OK, but I can't access SandyBridge machine at home now. Will try it next Monday.
> > Thanks, > > Ingo
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