Messages in this thread | | | Date | Mon, 23 May 2011 21:29:18 +0200 | Subject | Re: [PATCH 3/3] perf_events: add Intel Sandy Bridge offcore_response low-level support (v3) | From | Stephane Eranian <> |
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On Mon, May 23, 2011 at 6:21 PM, Peter Zijlstra <peterz@infradead.org> wrote: > On Mon, 2011-05-23 at 18:12 +0200, Stephane Eranian wrote: >> This patch adds Intel Sandy Bridge offcore_response support by >> providing the low-level constraint table for those events. >> >> On Sandy Bridge, there are two offcore_response events. Each uses >> its own dedictated extra register. But those registers are NOT shared >> between sibling CPUs when HT is on unlike Nehalem/Westmere. They are >> always private to each CPU. But they still need to be controlled within >> an event group. All events within an event group must use the same >> value for the extra MSR. That's not controlled by the second patch in >> this series. >> >> Furthermore on Sandy Bridge, the offcore_response events have NO >> counter constraints contrary to what the official documentation >> indicates, so drop the events from the contraint table. > > You sending this suggests you actually have a SNB machine, do you also > happen to know how to use those SNB RSP MSRs? Lin Ming and I were > wondering how to fill out the extra-regs for > snb_hw_cache_events_jds[C(LL)]. > You first need to describe what you want to measure with those generic events. Then, from that, we can try and find a match with the offcore_resp bits.
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