Messages in this thread | | | Subject | Re: [PATCH v1 RESEND] audio: tlv320aic26: fix PLL register configuration | From | Liam Girdwood <> | Date | Sat, 21 May 2011 12:08:22 +0100 |
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On Fri, 2011-05-20 at 10:26 -0400, Michael Williamson wrote: > The current PLL configuration code for the tlc320aic26 codec appears to assume a > hardcoded system clock of 12 MHz. Use the clock value provided by the DAI_OPS > API for the calculation. > > Tested using a MityDSP-L138 platform providing a 24.576 MHz clock. > > Signed-off-by: Michael Williamson <michael.williamson@criticallink.com> > Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> > --- > This got bounced by the alsa-devel list (I wasn't on list). I'm not sure > whose tree this needs to go through, but given the lack of response > I'm guessing alsa-devel. If I'm missing a list, any advice would be > appreciated.
Applied.
Thanks
Liam
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