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SubjectRe: [PATCH 1/3] mpt2sas: remove the use of writeq, since writeq is not atomic
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On Thu, 2011-05-19 at 08:46 +0400, James Bottomley wrote:
> This can't really be done generically. There are several considerations
> to do with hardware requirements. I can see some hw requiring a
> specific write order (I think this applies more to read order, though).

Right. Or there can be a need for a completely different access pattern
to do 32-bit, or maybe write only one half because both might have a
side effect etc etc etc ...

Also a global lock would be suboptimal vs. a per device lock burried in
the driver.

> The specific mpt2sas problem is that if we write a 64 bit register non
> atomically, we can't allow any interleaving writes for any other region
> on the chip, otherwise the HW will take the write as complete in the 64
> bit register and latch the wrong value. The only way to achieve that
> given the semantics of writeq is a global static spinlock.
>
> > How do you think about them? If you cannot agree with the above two
> > solutions, I'll agree with reverting them.
>
> Having x86 roll its own never made any sense, so I think they need
> reverting anyway.

Agreed.

> This is a driver/platform bus problem not an
> architecture problem. The assumption we can make is that the platform
> CPU can write atomically at its chip width. We *may* be able to make
> the assumption that the bus controller can translate an atomic chip
> width transaction to a single atomic bus transaction; I think that
> assumption holds true for at least PCI and on the parisc legacy busses,
> so if we can agree on semantics, this should be a global define
> somewhere. If there are problems with the bus assumption, we'll likely
> need some type of opt-in (or just not bother).

And we want a well defined #ifdef drivers test to know whether there's a
writeq/readq (just #define writeq/readq itself is fine even if it's an
inline function, we do that elsewhere) so they can have a fallback
scenario.

This is important as these can be used in very performance critical code
path.

Cheers,
Ben.



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