Messages in this thread |  | | | Date | Fri, 13 May 2011 08:46:18 -0700 | | Subject | Re: [PATCH 1/4] MIPS: Replace _PAGE_READ with _PAGE_NO_READ | | From | Kevin Cernekee <> |
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On Fri, May 13, 2011 at 8:07 AM, Ralf Baechle <ralf@linux-mips.org> wrote: >> Reuse more of the same definitions for the non-RIXI and RIXI cases. This >> avoids having special cases for kernel_uses_smartmips_rixi cluttering up >> the pgtable*.h files. >> >> On hardware that does not support RI/XI, EntryLo bits 31:30 / 63:62 will >> remain unset and RI/XI permissions will not be enforced. > > Nice idea but it breaks on 64-bit hardware running 32-bit kernels. On > those the RI/XI bits written to c0_entrylo0/1 31:30 will be interpreted as > physical address bits 37:36.
Hmm, are you sure? (Unfortunately I do not have a 64-bit machine to test it on.)
I did not touch David's existing build_update_entries(), which makes a point not to set the RI/XI bits when the RIXI feature is disabled:
if (kernel_uses_smartmips_rixi) { UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); if (r4k_250MHZhwbug()) UASM_i_MTC0(p, 0, C0_ENTRYLO0); UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); } else { UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ if (r4k_250MHZhwbug()) UASM_i_MTC0(p, 0, C0_ENTRYLO0); UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ if (r45k_bvahwbug()) uasm_i_mfc0(p, tmp, C0_INDEX); } If RIXI is enabled, it shifts the SW bits off the end of the register, then rotates the RI/XI bits into place.
If RIXI is disabled, it shifts the SW bits + RI/XI bits off the end of the register. It should not be setting bits 31:30 or 63:62, ever.
(A side issue here is that ROTR is a MIPS R2 instruction, so we could never remove the old handler and use the RIXI version of the TLB handler on an R1 machine.)
If setting EntryLo bits 31:30 for RI/XI is illegal on a 64-bit system running a 32-bit kernel, I suspect we will have a problem with the existing RIXI TLB update code, regardless of whether my changes are applied. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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