Messages in this thread | | | Date | Tue, 10 May 2011 17:29:11 +0200 | From | Ingo Molnar <> | Subject | Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events |
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* Peter Zijlstra <a.p.zijlstra@chello.nl> wrote:
> On Tue, 2011-05-10 at 22:17 +0800, Lin Ming wrote: > > > > I'm also not sure if the bits combination do count exactly > > L3_HIT/_MISS. > > > <snip manual bits> > > > May need some micro-benchmarks to verify it. > > either that or ask for clarification internally.
Well, please run micro-benchmarks to verify it in any case! Having more clarification than that will also be useful.
Thanks,
Ingo
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